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Data structures and circuit for multi-channel data transfers using a serial peripheral interface

A serial interface and data structure technology, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc.

Inactive Publication Date: 2008-12-24
QUICKFILTER TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The processor must also process each data sample independently

Method used

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  • Data structures and circuit for multi-channel data transfers using a serial peripheral interface
  • Data structures and circuit for multi-channel data transfers using a serial peripheral interface
  • Data structures and circuit for multi-channel data transfers using a serial peripheral interface

Examples

Experimental program
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Embodiment Construction

[0012] figure 2 The block diagram of the figure shows a multi-channel signal processing function module (100) executed independently of a system processor, and a serial interface controller (200) working according to a serial clock provided by the processor. figure 2 The signal processing functional module (100) shown in is an ADC and a filtering functional part, but it is obvious that the system and method disclosed herein can also be conveniently used to transmit high-speed, multi-channel data to the receiving processor. any application. Therefore the data source (100) does not have to be a digital filter system.

[0013] The serial interface communicates with the processor (not shown) via standard Serial Peripheral Interface (SPI) I / O signals used by many processors to communicate with peripheral devices, each of which may be a separate An integrated circuit or collection of integrated circuits to perform a desired processing function. For example, the processor could be...

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Abstract

A serial interface controller (200) provides for transferring data between a data source having a least one channel (110) and a processor. The serial interface controller (200) has a plurality of control registers (220); the control registers (220) in turn include a data structure for configuring the serial interface controller (200) for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller (200) in its run mode or its configuration mode; a field for storing the I / O mode of the serial interface controller (200); a field for storing the address of the active data channel; and, a field for storing the system clock rate. In the preferred embodiment, the control registers (220) include fields for device identification, a flag for the run or configure mode, a I / O-mode control, a value for the channels active (in multi-channel implementations), the data source clock rate, the ADC clock rate, channel-status flags, the CIC decimation rate, the number of taps for FIR filters, and the filter coefficients corresponding to the number of FIR taps in a particular data source.

Description

technical field [0001] The present invention relates to digital signal processing applications that require the use of multi-channel signal processing hardware interacting with a microprocessor or digital signal processor (DSP). The present invention provides a serial peripheral interface protocol and control procedures that minimize processor overhead while simultaneously transferring high data rate samples for further processing. Background technique [0002] The Serial Peripheral Interface (SPI) is an alternative messaging method that enables efficient communication between a processor and slave hardware devices, where a "stream" of data is transferred between the devices. SPI is a serial interface standard established by Motorola (now Freescale Semiconductor), which is supported in silicon products by several manufacturers. Its appeal lies in requiring a minimum I / O pin count and enabling different devices to implement a software communication protocol built on top of t...

Claims

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Application Information

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IPC IPC(8): G06F7/00
CPCG06F13/385G06F13/14G06F13/42G06F7/00
Inventor T·梅格德伯格A·黑德利
Owner QUICKFILTER TECH
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