Stacking encapsulation structure with symmetric multi-chip migration up and down

Abstract

The invention provides a multi-chip offset stacked package structure, which is symmetric on upper and lower sides. The multi-chip offset stacked package structure comprises a wire holder composed of a plurality of inner pin groups that are oppositely arranged and a chip bearing seat, wherein the chip bearing seat is positioned among the plurality of inner pin groups, and both the inner pin groups and the chip bearing seat have respective upper surfaces and low surfaces; a first multi-chip offset stacked package structure and a second multi-chip offset stacked package structure, which are respectively fixedly connected on the upper surface and the lower surface of the bearing seat of the chip; a plurality of metal wires for electronically connecting the first multi-chip offset stacked package structure and the second multi-chip offset stacked package structure with the inner pin groups; and a sealant for coating the first multi-chip offset stacked package structure, the second multi-chip offset stacked package structure, the inner pin groups and the bearing seat of the chip, and exposing outer pins.

Description

technical field [0001] The invention relates to a multi-chip stack package structure, in particular to a multi-chip offset stack package structure formed up and down symmetrically by chip holders. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end manufacturing process of semiconductors, hoping to use the least area to achieve higher density or memory capacity. In order to achieve this goal, a chip stacked method has been developed to achieve a three-dimensional (Three Dimension; 3D) package at this stage. [0003] In the known technology, the chip stacking method is to stack multiple chips on the substrate, and then use a wire bonding process to connect the multiple chips to the substrate. Figure 1A discloses a chip stack package structure based on a lead frame. As shown in Figure 1A, the lead frame 5 can be divided into an inner lead part 5a, an outer lead part 5b and a platform part 5c, wherein the platfor...

AI Technical Summary

Problems solved by technology

[0004] In the above-mentioned known chip stack package structure, in addition to the offset formed between the chips, which will cause uneven and uneven mold flow during injection molding; there are also metal wires between the chips, for example: in FIG. 1A 10, 11, 12 or 62 in Figure 1C, the length and radian of each metal wire are different, so except during the sealing process, metal wires with longer lengths and radians are prone to displacement and cause In addition to the short circuit of the chip, there will also be problems such as changes in the phase of the electrical signal due to the different lengths of the metal wires.

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