Encapsulation construction of multi-chip stack

Abstract

A packaging structure made through stacking a plurality of chips comprises a base plate and a multi-chip stacking structure; a plurality of metal end points are arranged on the base plate; the multi-chip stacking structure is made through stacking the plurality of chips, and is fixedly connected with the base plate through a first adhesive layer; an active surface of each chip in the multi-chip stacking structure is provided with a plurality of welding pads, and the active surface of the chip is connected with the back surface of another chip through a second adhesive layer to form a stackingstructure; the plurality of welding pads on the plurality of chips are electrically connected with the plurality of metal end points on the base plate through metal conducting wires; and all the chips used for forming the multi-chip stacking structure are stacked with each other by an offset, with one part of the welding pads on the active surface of each chip that is stacked below and the metal conducting wires exposed, and the other part of the welding pads and the metal conducting wires covered by the second adhesive layer.

Description

technical field [0001] The present invention relates to a multi-chip stacking package structure, in particular to a multi-chip stacking structure in which reverse bonding processes and insulating layers are used to reduce the curvature of metal wires, and the adhesive layer of the multi-chip stacking structure is added with a similar The encapsulation structure of the ball. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a method of using chip stacked (chip stacked) to achieve three-dimensional space (Three Dimension; 3D) packaging has been developed at this stage. [0003] In the known technology, the chip stacking method is to stack multiple chips on a substrate, and then use a wire bonding process to connect the multiple chips to ...

AI Technical Summary

Problems solved by technology

Obviously, this method of stacking packages with the spacer layer 130 cannot reduce the thickness of the stacked packages, so the number of chips that can be stacked is limited.

[0006] In the stacked package structure in FIG. 1 and FIG. 2, there is also a common problem, that is, the disposition position of the spacer 130 cannot give full support to the upper chip (120b; 20), so when performing wire bonding, If the chip is too thin, the chip may be broken during the wire bonding process (wafer broken)

Therefore, the chips in the stacked packaging structure using the spacer 130 need to have a certain thickness, so this stacked packaging structure cannot stack too many chips.

In addition, in the process of chip stacking, there may also be a problem that the upper chip (120b; 20) contacts the lower wire 140, resulting in a short circuit

In addition, in the stack package structure with the spacer 130, after the wire bonding process is completed, the injection molding (molding) is performed, but since the distance between the upper and lower chips is only the thickness of the spacer 130 or the spacer layer 50, Therefore, air bubbles (void) may be formed in the distance between the upper and lower chips. When the air bubbles are expanded by high temperature, it will cause cracks in the encapsulant.

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