Embedded heterogeneous chip multiprocessor on-chip communications interconnecting organization level accomplishing method

A heterogeneous multi-core, on-chip communication technology, which is applied in general stored-program computers and architectures with multiple processing units, can solve the problems of not considering the different characteristics and requirements of processing cores, and improve inter-core collaboration and Effects on Data Transfer Performance

Inactive Publication Date: 2008-10-22
ZHEJIANG UNIV
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Problems solved by technology

[0014] At the same time, the existing organizational levels do not take into account

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  • Embedded heterogeneous chip multiprocessor on-chip communications interconnecting organization level accomplishing method
  • Embedded heterogeneous chip multiprocessor on-chip communications interconnecting organization level accomplishing method
  • Embedded heterogeneous chip multiprocessor on-chip communications interconnecting organization level accomplishing method

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Embodiment Construction

[0035] The present invention is a kind of realization method of communication interconnection organization level on the chip of embedded heterogeneous multi-core system, combined below figure 1 Describe its specific implementation process.

[0036] 1) Classify processor cores:

[0037] According to the different functional characteristics of the processor cores in the embedded heterogeneous multi-core system, the on-chip processing cores are divided into two types: control-intensive processing cores and calculation-intensive processing cores.

[0038] A control-intensive processing core means that its primary function is system control. The instruction set (Instruction Set Architecture, ISA) of this kind of processing core is not oriented to computing. Operating systems, server applications, and I / O-intensive applications are all suitable fields for this type of processing core. Therefore, the control-intensive feature is that data calculation is only a small part of its ap...

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Abstract

The invention discloses a method for realizing communication interlinkage of organization levels on an embedded type heterogeneous polynuclear system chip. The method combines the characteristics of an embedded type heterogeneous polynuclear system structure and designs two internuclear buses of: a computation bus for connecting a computation-intensive nucleus and a control bus for connecting a control-intensive nucleus. At the same time, a memory controller is regarded as a processing nucleus and is connected to the computation bus, thereby unifying the control communication and data access communication between the processing nucleuses and between the processing nucleus and a memory in the chip. The method realizes the communication between a main nucleus and an auxiliary nucleus in a bus form, effectively improves the performances of internuclear cooperation and data transmission, faces to common multimedia processing, data comparison, signal coding and decoding, pattern matching and other computation-intensive processing of the embedded type polynuclear field and has strong practicability.

Description

technical field [0001] The invention relates to the field of embedded heterogeneous multi-core technology, in particular to a method for realizing on-chip communication and interconnection organizational levels of an embedded heterogeneous multi-core system. Background technique [0002] With the development of integrated circuit technology to the stage of deep submicron, the research of contemporary processor architecture is developing towards the direction of multi-core. Regardless of improving processor performance or considering the energy consumption factor of unit computing performance, multi-core architecture is a hot research direction at present. [0003] In the industry, Intel, IBM, AMD, SUN and other top international chip companies have released multi-core processors on the market. There are both homogeneous multi-core processors and heterogeneous multi-core processors. [0004] At present, the development of multi-core processors is still in its infancy, and t...

Claims

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Application Information

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IPC IPC(8): G06F15/80
Inventor 陈天洲胡威施青松严力科谢斌黄江伟章铁飞冯德贵项凌祥陈剑
Owner ZHEJIANG UNIV
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