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Double-stage self-aligning contact window and manufacturing method thereof

A manufacturing method and contact window technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., to achieve the effects of avoiding incomplete opening, increasing process space, and increasing production

Active Publication Date: 2013-05-22
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The invention provides an etching process for self-aligning contact windows, which can improve the alignment accuracy space (Aligned accuracy window) between the contact window and the gate, and solve the short circuit problem caused by misalignment and excessive etching expansion

Method used

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  • Double-stage self-aligning contact window and manufacturing method thereof
  • Double-stage self-aligning contact window and manufacturing method thereof
  • Double-stage self-aligning contact window and manufacturing method thereof

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Embodiment 1

[0054] Figure 2A to Figure 2F It is a flow sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0055] Please refer to Figure 2A , first provide a substrate 100 . The substrate 100 is, for example, a silicon substrate, such as an N-type silicon substrate or a P-type silicon substrate. Certainly, the substrate 100 may also be a substrate with silicon on an insulating layer or the like. Transistors 102 and 103 have been formed on the substrate 100 . The transistors 102 and 103 are, for example, N-channel metal oxide semiconductor devices (NMOS) or P-channel metal oxide semiconductor devices (PMOS).

[0056] The transistors 102 and 103 are formed by a gate dielectric layer 104 , a gate 106 , a spacer 114 and a source / drain region 110 , respectively. The gate dielectric layer 104 is located between the gate 106 and the substrate 100 . The material of the gate dielectric layer 104 may be composed of a sil...

Embodiment 2

[0074] Figures 3A to 3H It is a flow sectional view of another method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0075] Please refer to Figure 3A and 3B , according to the method described in the embodiment, the dielectric layer 122 on the substrate 100 is subjected to a first-stage patterning process, so as to form a lower opening 136 corresponding to the source / drain region 110 in the dielectric layer 122, The lower opening 166 corresponds to the gate 106 of the transistor 103 and the lower opening 186 corresponds to the gate 106 of the transistor 102 and the source / drain region 110 of the transistor 103 .

[0076] Please refer to Figure 3C After removing the photoresist layer 124 , a conformal liner material layer 150 is first formed on the substrate 100 to cover the dielectric layer 122 and the sidewalls and bottoms of the lower openings 136 , 166 and 186 . The material of the liner material layer 150 includes sil...

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Abstract

A preparation method for double-stage automatic aligning contact window includes: forming a first dielectric layer on a substrate having a contact region; forming a bottom opening in the first dielectric layer corresponding to the contact region; forming a second dielectric layer on the first dielectric layer; forming a upper opening in the second dielectric layer, wherein the upper opening automatically aligns to the bottom opening and communicates with the bottom opening, thereby forming an automatic aligning contact window opening; and finally forming a conductive layer in the automatic aligning contact window opening.

Description

technical field [0001] The present invention relates to an integrated circuit element and its manufacturing method, and in particular to a two-stage self-aligned contact (Self-aligned contact, SAC) and its manufacturing method. Background technique [0002] With the advancement of science and technology, the manufacturing of electronic components must increase the density to meet the trend of light, thin, short and small electronic components. In addition to reducing the size of the semiconductor device itself, the method of increasing the density can also be achieved by reducing the distance between the semiconductor devices. However, whether it is reducing the size of the semiconductor device itself or reducing the distance between semiconductor devices, some process problems will occur. [0003] For the process of self-aligned contact window, after the size of the contact window is reduced, its aspect ratio (Aspect ratio) increases, the difficulty of etching is high, and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/522
Inventor 周玲君陈铭聪曹博昭
Owner UNITED MICROELECTRONICS CORP
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