Electronic carrier board

Abstract

The disclosed electric carrier plate comprises: a main body, at least two welding mats set on body surface in pairs, a protective layer covering body surface and forming an opening opposite to the mat position, wherein there are at least two same side walls on the opening to expose the mats, the first one is set vertically to the mat arrangement direction, while the second one is parallel. This invention can avoid different area of exposed mats, prevents electric element standing on the plate, fills insulation material between element and plate efficiently, and overcomes problem that it cannot form flow-in groove for package resin on small-size passive element bottom.

Description

technical field [0001] The present invention relates to an electronic carrier board, in particular to an electronic carrier board applied in surface mount technology (Surface Mounted Technology, SMT). Background technique [0002] With the advancement of integrated circuit production technology, the design and production of electronic components continue to develop towards the trend of miniaturization, and because they have larger-scale and highly integrated electronic circuits, their product functions are also more complete. [0003] In this case, the electronic components that are traditionally placed using Through Hole Technology (Through Hole Technology; THT) cannot be further reduced in size, thus occupying such as printed circuit board (Printed Circuit Board; PCB), circuit board (circuitboard) ) or substrate (substrate) and other electronic carrier boards have a lot of space, and the plug-in assembly technology needs to drill holes on the electronic carrier board corre...

AI Technical Summary

Problems solved by technology

[0015] This technology is still limited by the low resolution of the photosensitive solder mask layer. When the limited pad spacing is less than 275 microns, it is impossible to form barrier strips 331, so it cannot be applied to 0201 passive components.

[0016] In addition, when the solder mask layer is offset, the wetting area of ​​the two solder pads will be unequal. As shown in Figure 3B, the area of ​​the original solder pad that can be soldered (exposed solder mask layer opening area ) is A*B, if the solder mask is shifted to the left by X microns (the traditional substrate process offset capability is 75 microns), the area of ​​the left pad will be B*(A+X), and the area of ​​the right pad will be B*(A-X), the area of ​​the two pads will have a difference of B*(A+X)-B*(A-X)=2BX, this different wetted area will lead to passive components soldered on the pad Tombstone occurs

[0017] Furthermore, in the technologies disclosed in the above-mentioned U.S. Patent No. 6,521,997 and No. 2005 / 0253231, in the face of the influence of the configuration of adjacent passive components, they cannot provide an effective solution to the problem that the solder paste between adjacent passive components may pass between the substrate surface and the solder resist layer. Problems such as mutual diffusion and contact between the gaps, resulting in solder protrusion phenomenon, and even lead to the short circuit of adjacent passive components

[0018] To sum up, how to provide an electronic carrier board, when the electronic components are placed on it, can avoid the generation of air holes, electrical bridging and solder protrusion problems caused by the gaps between the electronic components and the electronic carrier board, and at the same time It is an urgent problem to be solved in the industry to avoid problems such as the deviation of the opening forming the exposed pad due to the process accuracy and error, resulting in the tombstoning phenomenon caused by the different size and area of ​​the exposed pad.

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