Finite impulse response digit filter capable of configuring parameter

Abstract

The invention discloses a finite impulse response digit filter based on FPGA which can use computer to dynamic configure filtering parameters. The invention uses 10 bit A / D converter to execute A / D conversion, digit signals are input into the FPGA device, FIR filtering is carried out in the FPGA device, and the filtered data are transferred to an upper machine through USB2.0 bus. On the other hand, the upper machine transfers the configure parameters obtained by calculation to the FPGA device through USB2.0 bus, so as to realize the FIR filter with different windows and different cutoff frequency. A lower machine taking the FPGA as the kernel device can fulfill heavy data filtering work, alleviates the problem of the upper machine, and can satisfy the high-speed real-time requirement of the system; and because the upper machine can configure the key parameters of the operational procedure in the FPGA through the USB2.0 bus, the flexibility requirement of the system can be satisfied.

Description

technical field [0001] The invention relates to a digital filter, specifically a finite impulse response digital filter with configurable parameters. technical background [0002] At present, the FIR digital filter can be implemented by software, such as a computer program; or by hardware, such as DSP or FPGA. Among them, the digital filter implemented by computer program can easily adjust the filter characteristics, but the amount of data calculation is large, which takes up system resources. The FIR filter implemented by DSP device is relatively simple and widely used. The disadvantage is that the program is executed sequentially. Although the performance of DSP device is continuously improved, it is still limited in some occasions with high real-time requirements; FPGA device is a hardware parallel structure. , so the parallel iterative algorithm of the digital filter is very suitable to be realized by FPGA, but the common problem is that the filter coefficient of the fi...

AI Technical Summary

Problems solved by technology

Among them, the digital filter implemented by computer program can easily adjust the filtering characteristics, but the amount of data calculation is large, which takes up system resources.

The FIR filter implemented by DSP device is relatively simple and widely used. The disadvantage is that the program is executed sequentially. Although the performance of DSP device is continuously improved, it is still limited in some occasions with high real-time requirements; FPGA device is a hardware parallel structure. , so the parallel iterative algorithm of the digital filter is very suitable to be realized by FPGA, but the common problem is that the filter coefficient of the filter cannot be dynamically adjusted according to the characteristics of the filtered signal, and the filtering work of a single characteristic can only be completed, so the digital filter cannot be fully utilized. Technical advantages of flexible and adjustable filters

However, this method cannot adjust the parameters of the filter in real time, and it is not flexible enough to use.

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