Method for making non-volatile memory

Abstract

The invention relates to a fabricating method of a non-volatile memory. The method comprises the following steps: a substrate is provided firstly, and the substrate is provided with a source electrode line region. Secondly, a tunneling dielectric layer, a first conductor layer, an inter-gate dielectric layer and a second conductor layer are formed on the substrate in sequence. Thirdly, the second conductor layer and the inter-gate dielectric layer which are in the source electrode line region are removed, to ensure the first conductor layer to be exposed out. Fourthly, openings are formed in the first conductor layer which is in the source electrode line region and the tunneling dielectric layer. Fifthly, a third conductor layer is formed on the substrate, and the third conductor layers are filled into openings. Sixthly, the patterned process is performed, the third conductor layer , the second conductor layer, the inter-gate dielectric layer and the first conductor layer are all patterned, so as to form a plurality of stacked gate structures, and simultaneously a source electrode line is formed in the source electrode line region. Finally, doped regions are formed at the both sides of the stacked gate structures and in the substrate below the source electrode line.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor element, and in particular to a manufacturing method of a nonvolatile memory. Background technique [0002] Non-volatile memory has the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure, so it has become widely used in personal computers and electronic devices. A type of non-volatile memory used. [0003] A typical non-volatile memory is generally designed with a stacked gate structure, including a floating gate and a control gate made of doped polysilicon. The floating gate is located between the control gate and the substrate, and is in a floating state, not connected to any circuit, while the control gate is connected to the word line (word line), and also includes a tunnel oxide layer A tunneling oxide layer and an inter-gate dielectric layer are located between the substrate and the floating gate and...

AI Technical Summary

Problems solved by technology

[0006] Since the above-mentioned source lines and contact plugs are formed, photolithography (photolithography), etching (etching) and chemical mechanical polishing (CMP) processes will be performed multiple times, so the process steps will be more complicated. complex

In addition, complex process steps and the use of a large number of masks will also lead to increased production costs

Furthermore, a multi-layer dielectric layer is formed in the process, and the thickness of the dielectric layer is increased in order to avoid the coupling effect (coupling effect) between the bit line and the source line, which also increases the total thickness of the dielectric layer, so that Voids are easily generated in the contact plug and cause an increase in the resistance value of the device

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