Electrical device, memory device, and semiconductor integrated circuit

A technology of storage devices and electrical components, applied in the direction of electrical components, semiconductor devices, circuits, etc.

Inactive Publication Date: 2008-04-09
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

-Solution to the problem-

Method used

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  • Electrical device, memory device, and semiconductor integrated circuit
  • Electrical device, memory device, and semiconductor integrated circuit
  • Electrical device, memory device, and semiconductor integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

The electric element of the first embodiment of the present invention will be described below. And, as shown in FIG. 9, the circuit symbols of the electric elements used in this embodiment are defined. In FIG. 9, the upper electrode 1 of FIG. 1 is connected to a terminal 101-1. On the other hand, the lower electrode 3 of FIG. 1 is connected to the terminal 101-2.

[0069] As shown in FIG. 10 , when an electric pulse (positive polarity pulse) of "positive polarity" is applied to the electric element 102 with respect to the terminals 101-2 and 101-1, the resistance value of the electric element 102 decreases. Conversely, when an electric pulse (negative polarity pulse) of "negative polarity" is applied to the electric element 102 with respect to the terminals 101-2 and 101-1, the resistance of the electric element 102 increases. In other words, when an electric pulse is applied by causing a current to flow in the direction of the arrow, the resistance of the electric element...

no. 2 example

FIG. 12 shows the overall structure of a storage device 200 according to the second embodiment of the present invention. This device 200 has a memory array 201 , an address buffer 202 , a control unit 203 , a row decoder 204 , a word line driver 205 , a column decoder 206 , and a bit line / plate line driver 207 .

[0079] The memory array 201 is provided with word lines W1, W2, bit lines B1, B2, plate lines P1, P2, transistors T211, T212, T221, T222, and memory cells MC211, MC212, MC221, MC222. Memory cells MC211 to MC222 are electrical elements 102 shown in FIG. 9 .

[0080] The connection relationship between the transistors T211 to T222 and the memory cells MC211 to MC222 is the same, and the connection relationship between the transistor T211 and the memory cell MC211 will be described as a representative. The transistor T211 and the memory cell MC211 are connected in series between the bit line B1 and the plate line P1. Transistor T211 is connected between bit line B1 ...

no. 3 example

[0118]

[0119] [Write processing]

[0120] The logic circuit 301 outputs a mode selection signal MODE indicating "storage mode" to the control unit 203 of the memory circuit 200 in order to write predetermined data (for example, encrypted moving image data) into the memory device 200 .

[0121] Next, the logic circuit 301 sequentially outputs an address signal ADDRESS to the address buffer 202 of the memory device 200 in order to select a memory cell in which the predetermined data is to be written. Thus, in the memory device 200, the memory cells corresponding to the address signal ADDRESS are sequentially selected.

[0122] Next, the logic circuit 301 outputs the predetermined data of 1 bit each to the control unit 203 of the storage device 200 as 1-bit data Din.

[0123] Next, in the storage device 200, the same operations as in the storage mode of the second embodiment are performed. As a result, the predetermined data is written into the storage device 200 by 1 bit e...

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Abstract

An electric element includes a first terminal (1), a second terminal (3), and a variable-resistance film (2). The variable-resistance film (2) is connected between the first terminal (1) and the second terminal (3). The variable-resistance film (2) includes Fe3O4 crystal phase and Fe2O3 crystal phase.

Description

technical field [0001] The present invention relates to an electric element, a memory device and a semiconductor integrated circuit using a variable resistance material whose resistance increases / decreases according to a prescribed electric pulse. Background technique [0002] In recent years, with the development of digital technology in electronic equipment, in order to store data such as images, it is increasingly required to increase the capacity of non-volatile memory elements and to speed up data transfer. For such requirements, US Patent No. 6,204,139 clearly proposes the use of perovskite (peroVskite) materials (such as Pr (1-X) Ca X MnO 3 (PCMO), LaSrMnO 3 (LSMO), GdBaCo X o Y (GBCO)) and other technologies that constitute non-volatile memory elements. That is, these materials (hereinafter referred to as variable resistance materials) are given a predetermined electric pulse to increase or decrease their resistance value, and the changed resistance value is us...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/10H01L45/00H01L49/00
CPCH01L27/2436G11C2213/32H01L45/145H01L27/24G11C13/0007H01L45/146H01L27/101H01L45/04H01L45/1625H01L45/1233H10B63/30H10N70/20H10N70/826H10N70/8833H10N70/026
Inventor 三谷觉小佐野浩一村冈俊作名古久美男
Owner PANASONIC CORP
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