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Method for forming isolation structure of shallow plough groove

A trench isolation and trench technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of complicated process and unavoidable sidewall over-etching of the trench 70

Inactive Publication Date: 2008-04-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the method for forming the isolation trench is complex in process, and the over-etching of the sidewall of the trench 70 cannot be avoided in the process of removing the pad oxide 62.

Method used

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  • Method for forming isolation structure of shallow plough groove
  • Method for forming isolation structure of shallow plough groove
  • Method for forming isolation structure of shallow plough groove

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Embodiment Construction

[0037] The present invention provides a method for forming a trench isolation structure. In a specific embodiment of the present invention, the method includes the following steps:

[0038] sequentially forming a pad oxide layer and a corrosion barrier layer on the semiconductor substrate, and sequentially defining the corrosion barrier layer, the pad oxide layer, and the semiconductor substrate to form trenches;

[0039] forming a liner oxide layer on the inner surface of the trench;

[0040] forming an isolation oxide layer filling the trench and covering the sidewalls of the pad oxide layer and the etch barrier layer;

[0041] planarizing the isolation oxide layer to expose the corrosion barrier layer;

[0042] Remove the corrosion barrier layer and the pad oxide layer on the semiconductor substrate in turn; after the corrosion barrier layer and the pad oxide layer are removed, a depression will be produced on the side wall of the trench, and in order to fill the depressio...

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Abstract

A formation method for shallow groove isolation structure comprises the following steps that: a pad oxide layer and a corrosion barrier layer are orderly formed on a semiconductor basal plate, and the corrosion barrier layer, the pad oxide layer and the semiconductor basal plate are orderly defined to form a groove; a liner oxide layer is formed on the surface of the groove; an isolation oxide layer filling up the groove and covering the sidewalls of the pad oxide layer and the corrosion barrier layer is formed; the isolation oxide layer is flattened until the surface of the corrosion barrier layer is exposed; the corrosion barrier layer and the pad oxide layer are orderly removed; a rotary oxide layer is formed on the semiconductor basal plate and the isolation oxide layer to fill up the groove sidewall depressions of an isolation structure; the rotary oxide layer is removed until the semiconductor basal plate and the isolation oxide layer are exposed. The present invention avoids the defect of forming the depressions of the groove sidewall.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing process, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] Semiconductor integrated circuits generally contain active regions and isolation regions between the active regions, which are formed prior to fabrication of the active devices. The methods for forming isolation regions in the prior art mainly include local oxidation isolation process (LOCOS) or shallow trench isolation process (STI). The LOCOS process is to deposit a layer of silicon nitride on the surface of the wafer, and then perform etching to oxidize and grow silicon oxide on part of the recessed area. Active devices are grown in areas defined by silicon nitride. However, there is a "bird's beak" phenomenon of silicon nitride edge growth in the local oxidation isolation, as shown in Figure 1, which is caused by the difference in thermal expansion between si...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76232H01L21/7621
Inventor 辜良智魏峥颖朱赛亚翁健
Owner SEMICON MFG INT (SHANGHAI) CORP
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