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Simultaneous core testing in multi-core integrated circuits

A technology of integrated circuits and logic cores, applied in the field of structural testing of multi-core integrated circuits

Active Publication Date: 2008-03-19
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to pin constraints, only one core can be tested at a time

Method used

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  • Simultaneous core testing in multi-core integrated circuits
  • Simultaneous core testing in multi-core integrated circuits
  • Simultaneous core testing in multi-core integrated circuits

Examples

Experimental program
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Embodiment Construction

[0032] FIG. 1 illustrates a system for testing an integrated circuit including multiple logic cores, according to one embodiment. In one embodiment, a device under test (DUT) may be a chip multiprocessor, and cores 0 to N may be the same. The DUT may also include other circuits not included in the core. For example, the DUT may include bridging and / or memory control functions that allow the core to access common memory or other resources. In some cases, the base core that is duplicated in the multi-core DUT can be included in a previously developed single core IC. For example, a microprocessor chip containing only core 0 and the other functional blocks of the DUT may have been previously fabricated and tested using the automated test equipment (ATE) shown in FIG. 1 . In this case, it is best to use the same ATE that was used to test the previous IC, and test the DUT with minimal changes to hardware and software and without increasing test pattern size or test time.

[0033]...

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Abstract

Various embodiments of methods and systems for simultaneously testing multiple cores included in an integrated circuit are disclosed. In one embodiment, an integrated circuit may include two or more logic cores. The IC may also include structural scan test hardware coupled to the cores. This structural scan test hardware may be capable of inputting scan test vector data into scan registers associated with each of the logic cores, simultaneously executing a scan test on the logic cores included in the IC, and outputting the results of the scan tests for multiple cores to automated test equipment (ATE) simultaneously. In one embodiment, elements of the results of testing for multiple cores may be interleaved on a single output line such that an element of test result data from each core is present on an input channel to the ATE during each strobe window.

Description

technical field [0001] The present invention relates to the field of integrated circuit (Integrated Circuit; IC for short) testing, especially related to the structural testing of multi-core integrated circuits such as multi-core microprocessors. Background technique [0002] Functional testing is typically used to test low to medium complexity integrated circuits (ICs). In some cases, a test vector may be developed to test all functional characteristics of a particular IC and used in manufacturing to verify each unit. Many ICs, such as Chip MultiProcessor (CMP), may be too complex for this approach, and the entire collection of functional test vectors (collection offfunctional test vectors) required for functional testing is not sufficient for commercially available automated test Equipment (Automated TestEquipment; ATE for short) may be too large. [0003] Most ICs contain a set of independent or semi-independent functional blocks, and in some cases it may be more effici...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318563G01R31/3185
Inventor T-Y·郭D·K·埃尔维
Owner ADVANCED MICRO DEVICES INC
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