Dynamically synchronizing a processor clock with the leading edge of a bus clock

Abstract

Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. The detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein. The method includes generating a bus clock and a processor clock without a corresponding control signal, receiving an insertion-delayed version of the bus clock and processor clock, and processing the insertion-delayed bus clock and processor clock to generate a flag signal that indicates the location of a leading edge of the insertion-delayed bus clock.

Description

technical field [0001] The present invention relates to a processor or a microprocessor in a computer system or a system-on-chip (SOC) device, in particular to a circuit combined with a processor for detecting the leading edge of a bus clock (leading edge) to dynamically synchronize the higher frequency processor clock with the lower frequency bus clock. Background technique [0002] Computer systems usually advertise product performance based on various characteristics of the processor, especially the processor's internal clock. In general, the frequency of the processor clock will be many times higher than the frequency of the bus clock, so although the processor can usually operate at the fast clock speed as advertised in the data sheet, many processor clocks have no direct impact on the bus and peripherals. Too fast for the device. Therefore, these processors can only communicate with peripheral devices at lower interface bus speeds. Even in system-on-chip (SOC) device...

AI Technical Summary

Problems solved by technology

As mentioned earlier, this technique of using a central clock control circuit has the disadvantage of misaligning the bus and processor clocks when the control signal is at the terminal node, resulting in the inability to properly synchronize the bus and processor clocks, so it needs to be done manually Adjustments to remove errors

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