Method and apparatus for memory access scheduling to reduce memory access latency

Abstract

A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Description

technical field [0001] The present invention relates to memory controllers, and more particularly, to methods and apparatus for reducing memory access latency and increasing bandwidth. Background technique [0002] Modern memories, such as dynamic random access memory (DRAM), are used throughout the computer industry. Memory is organized into pages. Each memory page contains data in a number of contiguous memory cells. Memory devices such as DRAM are further organized into a small number of banks (eg, 4 banks) for each DRAM device. Each of these devices has many pages for each memory block. Only a single page can be accessed from a memory block at a time. Before a page in a memory block can be accessed, the page must be opened using the "activate" command. This activation command is also called a "row" command. A memory request that requires an open page is called a page-empty access request. A memory request for a page that has already been opened is called a page-hi...

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Problems solved by technology

If these free DRAM command bus slots are not otherwise used, then this can lead to memory system efficiency and performance degradation

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