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Multidimensional array rapid read-write method and apparatus on dynamic random access memory

A technology of dynamic random access, reading and writing methods, applied in static memory, digital memory information, information storage, etc., to achieve the effect of saving storage space

Inactive Publication Date: 2009-09-09
XIAOSHAN IND RES INST
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  • Claims
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Problems solved by technology

[0005] The problem is even more serious for two-dimensional arrays

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  • Multidimensional array rapid read-write method and apparatus on dynamic random access memory
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  • Multidimensional array rapid read-write method and apparatus on dynamic random access memory

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Embodiment Construction

[0041] First analyze the read and write rules of DRAM. Each DRAM chip generally has 2 or 4 banks, and each bank is an array of memory cells organized in rows and columns. DRAM access includes three parts: row selection, column selection and precharge (precharge). Row selection is to give the DRAM chip an active (activation) command and row address, after t RCD At this time, the row of data represented by the row address will be copied to the row buffer inside the chip. Column selection is to read and write data on the row buffer according to the column address. Because the reading and writing are all on the row buffer when selecting the column, the speed is very fast. No matter whether the given column address is continuous or not, the data pin can transmit one number in one clock cycle (DDR can transmit two numbers in one clock cycle), such as figure 1 and figure 2 shown, but only if the data to be accessed is in the currently open DRAM row. If the data to be accessed i...

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Abstract

The invention discloses a fast reading and writing method of a two-dimensional array on a DRAM. Firstly, according to the capacity C of one row of the DRAM and the ratio I / J of the number of reads and writes of data by row and by column, determine the plurality of same sizes that the two-dimensional array is divided into. The number of columns A=(CI / J)1 / 2 and the number of rows B=(CJ / I)1 / 2 of the sub-matrix; when writing the two-dimensional array by row or column on the DRAM, each relevant A× The data belonging to the row or column of the B sub-matrix is ​​respectively written on a row of the DRAM in order; when reading a two-dimensional array on the DRAM by row or column, the relevant rows on the DRAM are selected one by one through the address change, each time All required data in one row is read out, and then the next row is selected. The control logic unit of the DRAM of the present invention includes an address generator, and the address generator generates addresses required for reading and writing two-dimensional arrays on the DRAM according to parameter values. The invention can also be used for reading and writing of multi-dimensional arrays, which can save the space and time required for transposition and improve the reading and writing speed.

Description

technical field [0001] The invention relates to a method for reading and writing a dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM), in particular to a method for reading and writing two-dimensional or more than two-dimensional arrays on the dynamic random access memory. Background technique [0002] In current computer applications, two-dimensional arrays are often processed, such as image processing, radar and sonar digital signal processing, machine vision and image tracking, synthetic aperture radar imaging, coordinate conversion, etc. Two-dimensional arrays are currently stored in one-dimensional form on the storage system of the computer, that is, from the physical address of the storage system, if the data in the row direction of the two-dimensional array is stored continuously, the data in the column direction is stored non-contiguously. of. This discontinuous storage makes it impossible to use certain fast read and write methods for ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/409G11C7/00
Inventor 莫志锋韩承德王贞松
Owner XIAOSHAN IND RES INST
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