Self-correcting circuit for mismatch capacity

Abstract

The invention relates to a capacity unmatched automatic correct circuit, which comprises sampling hold circuit, comparer, and switch control circuit, wherein the sampling hold circuit comprises compensating capacitor array, target capacity, and reference capacity, to provide output voltage; said output voltage is the calculation result of equivalent capacitor, target capacitor, and reference capacitor; the comparer via the output voltage of sampling hold circuit provides compare signal; the switch control circuit provides compensating control signal to the compensating capacitor array ton control the equivalent capacitor of said array, and in each period of time pulse signal, based on the compare signal, adjusts the compensating control signal, adds target capacitor on the equivalent capacitor, to reach reference capacitor along the time pulse signal.

Description

technical field [0001] The present invention relates to a capacitance mismatch automatic correction circuit, and in particular to a progressive capacitance mismatch automatic correction circuit. Background technique [0002] In integrated circuits, matching of capacitance values ​​is often an important design consideration. Such as switch-capacitor circuit (switch-capacitor circuit) and digital-to-analog converter (DAC: digital-to-analog converter), etc., may limit the performance of the circuit due to capacitance mismatch caused by process offset, causing the circuit to fail to perform original design level. Therefore, for integrated circuit design, how to compensate the capacitance mismatch caused by the process shift, so that the designed circuit can exert its original effectiveness and accuracy is an important key. [0003] Most of the conventional technologies use an additional capacitor array formed in parallel with the original capacitor to compensate for the mismat...

AI Technical Summary

Problems solved by technology

[0005] First, the original design requires a sample hold and switching circuit 102, which includes an S / H circuit and a switching circuit at any time, which increases the complexity of the circuit design

[0006] Second, the DAC 104 must generate multiple analog voltages corresponding to the digital codes for comparison. The voltage source and accuracy of this design are problems, and the circuit complexity is high

[0007] Third, this method needs to perform complicated correction steps for each digital code, the required clock pulse operation time is long, and the hardware implementation area of ​​the digital circuit is relatively large

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