Pushed-rule bit cells with new functionality

Abstract

A memory bit cell suitable for use in semiconductor integrated circuits that utilizes pushed design rules and layout geometries optimized by a semiconductor foundry for standard memory bit cells and edge-cell structures that provides a different functionality from that provided by the foundry standard bit cell. This different functionality is achieved by interconnecting the elements of one or a plurality of standard foundry bit cells and edge cells to implement a different circuit with different operation from the original bit cells and edge cells. The positioning and interconnection of the standard bit cells and edge cells are implemented in a manner so as to maintain the same periodic geometric proximity effects to the maximum degree possible. A preferred embodiment of this invention is to interconnect two standard foundry six-transistor SRAM bit cells and two edge cells to create a Ternary Content Addressable Memory bit cell with mask and compare functionality in addition to bit storage functionality.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of provisional patent application entitled Provisional Patent Application for Pushed-rule Bit Cells with New Functionality filed 2008 Nov. 24, Application No. 61 / 200,146 by the present inventor.FEDERALLY SPONSORED RESEARCH[0002]Not ApplicableSEQUENCE LISTING OF PROGRAM[0003]Not ApplicableBACKGROUND OF THE INVENTION[0004]1. Field of Invention[0005]This invention relates to the design and layout of semiconductor memory bit cells using design rules that are smaller than the standard logic design rules for a given process technology node in order to reduce area per bit and improve performance.[0006]2. Prior Art[0007]Prior art for many types of memory bit cells such as Content Addressable Memories (CAMs) and Register File Memories use bit cells laid out using the standard logic design rules for a given process technology node such as 28-nanometer. This has the advantage that the design rules are proven to pr...

AI Technical Summary

Benefits of technology

This patent is about improving layouts for memory bit cells in semiconductor integrated circuits to make them smaller, perform better, and use less power than standard layout rules. It takes advantage of pushed layout design rules developed for standard memory bit cells to create new bit cells with different functionality. The invention is particularly useful for creating bit cells for ternary content addressable memories (TCAMs), which require a unique layout design. By arranging the bit cells and their neighbors in a specific way, the invention allows for more efficient manufacturing, better performance, and lower power consumption. Overall, this patent provides a technical solution for creating more efficient and effective memory bit cells.

Problems solved by technology

Often memory performance also limits the maximum frequency of operation of integrated circuits and memory power dissipation is a major contributor to overall power dissipation of integrated circuits.

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