Hybrid carbon [nanotude] nanotube FET(CNFET)-FET static RAM (SRAM) and method of making same

Abstract

Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Description

CROSS-REFERENCE OF RELATED CASES[0001]This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 60 / 644,427, filed on Jan. 14, 2005, entitled Field Effect Device Having a Channel of Carbon Nanofabric and Method of Making Same, and U.S. Provisional Patent Application No. 60 / 644,641, filed on Jan. 18, 2005, entitled Hybrid Carbon Nanotubes FET (CNFET)-FET Static RAM (SRAM), the contents of which are hereby incorporated by reference in their entireties.[0002]This application is related to U.S. patent application Ser. No. 11 / 332,529, filed on an even date herewith, entitled Field Effect Device Having a Channel of Nanofabric and Methods of Making Same, the contents of which is hereby incorporated by reference in its entirety.BACKGROUND[0003]1. Technical Field[0004]This invention relates in to a field effect device having a channel of carbon nanofabric, a static random access memory (SRAM) made of such, and a method of making the same.[0005]2. D...

AI Technical Summary

Problems solved by technology

A major problem was that NMOS devices were in the ON state as fabricated.

Positive ions both fixed and mobile, combined with the work function of the aluminum gate and p-substrate doping, plus defects in the Si / SiO2 interface made it impossible to find a fabrication-only solution to the fabricated normally-ON NMOS problem (it took well over 10 years to find a fabrication-only solution).

Layout ground rules require separation between the P+ diffusions of PFET devices and the P substrate region, and separation between the N+ diffusions of NFET devices and the NWELL region results in a larger cell area and complicates scaling of cell size as technology dimensions shrink.

However, if the voltage on nodes 2520 and 2530 exceed T2 and T4 threshold voltages, these devices will provide an additional path for burn-off current, but too small a burn-off current to provide a significant increase in current carrying capability.

The SRAM product circuits such as word decode, bit decode and sense amplifier, timing circuits, etc. are not fully wired at this point and are not powered.

Some density gain due to stacking of P-CNFET devices may be lost; however, cell stability is increased because of additional node capacitance.

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