Delay time calculation apparatus and integrated circuit design apparatus

Abstract

A delay time calculation apparatus includes a resistance-capacitance determining section for determining a source resistance and a diffusion capacitance of a target gate of a delay time calculation before a process variation, and a wiring resistance and a wiring capacitance of a wire connected to the gate after the process variation. The delay time of the gate is calculated according to the results the resistance-capacitance determining section obtains. It can solve a problem of a conventional apparatus in that although the conventional apparatus can calculate the delay time of the gate accurately as long as the process variation coefficients for the cell delay and wire delay match the target gate of the delay time calculation, it becomes increasingly difficult to calculate the delay time accurately with an increase in the error of the process variation coefficients.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a delay time calculation apparatus for calculating the delay time of a gate after a process variation and to an integrated circuit design apparatus using the same.[0003]2. Description of Related Art[0004]A semiconductor integrated circuit is composed of a plurality of gates. A delay time of each gate (called “gate_delay” from now on) is defined as a sum of a delay time occurring within the gate (called “cell_delay” from now on) and a delay time (called “wire_delay” from now on) occurring in wire connected to the gate.[0005]FIG. 10 is a schematic diagram illustrating a gate delay gate_delay(typ) in a typical condition, in which the delay time is typical (see, expression (1)); FIG. 11 is a schematic diagram illustrating a gate delay gate_delay(max) in a maximum condition, in which the cell delay is maximum (see, expression (2)); and FIG. 12 is a schematic diagram illustrating a gate delay ...

AI Technical Summary

Benefits of technology

[0032]The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a delay time calculation apparatus and integrated circuit design apparatus capable of calculating the delay time of a gate accurately.

[0033]According to a first aspect of the present invention, there is provided a delay time calculation apparatus including: a resistance-capacitance determining section for determining, referring to the placement and routing results obtained by a placement and routing result acquiring section, a source resistance and a diffusion capacitance of a target gate of delay time calculation before a process variation, and a wiring resistance and a wiring capacitance of a wire connected to the gate after the process variation; and a delay time calculating section for calculating the delay time of the gate according to results determined by the resistance-capacitance determining section. Thus, it offers an advantage of being able to calculate the delay time of the gate accurately.

[0034]According to a second aspect of the present invention, there is provided an integrated circuit design apparatus including: a resistance-capacitance determining section for determining, referring to the placement and routing results obtained by a placement and routing result acquiring section, a source resistance and a diffusion capacitance of a target gate of delay time calculation before a process variation, and a wiring resistance and a wiring capacitance of a wire connected to the gate after the process variation; a delay time calculating section for calculating the delay time of the gate according to results determined by the resistance-capacitance determining section; and a verifying section for verifying the placement and routing results by the placement and routing section, referring to the delay time calculated by the delay time calculating section. Thus, it offers an advantage of being able to alter the placement and the like if the results of the placement and routing have something unsatisfactory.

Problems solved by technology

However, the conventional delay time calculation apparatus calculates the gate delay time after the process variation without using the actual values after the process variation.

Although it can calculate the delay time of the gate accurately when the process variation coefficients KPcell(max) and KPcell(min) for the cell delay and the process variation coefficients KPWire(max) and KPWire(min) for the wiring match the target gate of the delay time calculation, it cannot calculate the delay time of the gate when the errors of the process variation coefficients increase.

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