Computing architecture with peripherals

Abstract

A shared memory computing device optimised for worst case execution time analysis that has at least one interconnect master, N cache modules and N processor cores. Each cache module has a finite state machine that employs an update-type cache coherency policy. Each processor core is assigned a different one of the N fully associative cache modules as its private cache. Furthermore, the execution time of memory transfer requests issued by each of the N processor cores is not modified by: (a) the unrelated memory transfer requests issued by any of the other N processor cores; or (b) the unrelated memory transfer requests issued by at least one other interconnect master.

Description

FIELD OF THE INVENTION[0001]The present invention relates to multi interconnect master computing architectures and is particularly applicable to real-time and mixed-criticality computing involving peripherals.BACKGROUND OF THE INVENTION[0002]Throughout this specification, including the claims:[0003]a bus master is a type of interconnect master;[0004]to a bus target / stave is a type of an interconnect target;[0005]a memory store coupled with a memory controller may be described at a higher level of abstraction as a memory store;[0006]a peripheral may or may not have I / O pins;[0007]a peripheral is connected to an interconnect that transports memory transfer requests;[0008]a peripheral may be memory mapped, such that a memory transfer request to the interconnect target port of a peripheral is used to control that peripheral;[0009]a processor core may be remotely connected to an interconnect over a bridge; and[0010]a definition and description of domino timing effects can be found in [1]...

AI Technical Summary

Problems solved by technology

Many shared memory computing devices with multiple bus-masters / interconnect-masters, such as the European Space Agencies' Next Generation Microprocessor architecture [3] experience severe real-time problems [4].

For example, unwanted timing interference can occur by memory transfer requests issued by other cores and bus master peripherals to the level 2 cache module and SDRAM.

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