Programmable logic device and method for manufacturing semiconductor device

Abstract

To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a programmable logic device with which the configuration of hardware can be changed and a method for manufacturing a semiconductor device using the programmable logic device.[0003]2. Description of the Related Art[0004]In a semiconductor device called a programmable logic device (PLD), a logic circuit is composed of an adequate number of programmable logic elements (basic blocks), and the function of each programmable logic element and interconnections between the programmable logic elements can be changed after manufacture. PLDs show flexibility in a reduction in development period and a change in design specification as compared with conventional application specific integrated circuits (ASICs) and gate arrays, which is advantageous, thus being widely used in recent years.[0005]The PLD needs a memory device for storing data (configuration data) on the function of each programmable logi...

AI Technical Summary

Benefits of technology

The present invention aims to provide a programmable logic device with a reduced number of elements per bit in its memory array. This allows for accurate power consumption and operation frequency estimation during the testing phase of the device. Additionally, the invention provides a manufacturing method for a semiconductor device that enables accurate power consumption and operation frequency estimation using the programmable logic device. The use of a transistor with small off-state current as a switch can further reduce power consumption and leakage of charge held in a node, leading to accurate power consumption estimation.

Problems solved by technology

However, in the configuration of Non-Patent Document 1, the SRAM having a large number of elements per bit is formed over the CMOS logic circuit; thus, defects are likely to be caused, which makes it difficult to manufacture a PLD with high yield.

Moreover, an SRAM composed of polysilicon TFTs not only consumes power in an operating state, but also consumes more than a little power in a non-operating state owing to the off-state current of the polysilicon TFTs, and power consumed by the PLD includes the power consumed by the SRAM.

Therefore, power consumption of a semiconductor device that is manufactured based on the PLD cannot be estimated accurately at the stage of testing the PLD.

Therefore, operation delay and power consumption due to parasitic capacitance between various wirings also cannot be estimated accurately at the stage of testing the PLD.

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