System and method for managing timing margin in a hierarchical integrated circuit design process

Abstract

A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.

Description

TECHNICAL FIELD[0001]This application is directed, in general, to integrated circuit (IC) design and, more specifically, to a system and method for managing timing margin in a hierarchical integrated circuit (IC) design process.BACKGROUND[0002]Modern digital logic devices offer unprecedented performance. For a variety of digital ICs, speed, level of integration (i.e., transistor density) and capabilities have improved. Moreover, in many cases, these performance improvements have been accompanied by reductions in size, power consumption and cost of the devices. However, these benefits have required greater complexity in digital logic design. Because of this complexity, the investment of time and resources by the manufacturer to design and fabricate a digital logic device has increased. For this same reason, the possibility of a mistake or oversight on the part of the designer has become more likely, and costlier to correct.[0003]As digital logic devices have continued to evolve, hier...

AI Technical Summary

Benefits of technology

The patent text describes a system and method for generating block timing constraints and a timing model. The system includes a hierarchical modeling tool that generates a model file and receives various inputs such as an abstracted view margin, timing environment margin, and operational margin. The tool then generates the block implementation timing constraints and a block timing model based on the abstracted view margin and operational margin. The technical effect of this invention is that it provides a more efficient and effective way to generate block timing constraints and a timing model, which can aid in the development of various applications such as video games and video content production.

Problems solved by technology

However, these benefits have required greater complexity in digital logic design.

Because of this complexity, the investment of time and resources by the manufacturer to design and fabricate a digital logic device has increased.

For this same reason, the possibility of a mistake or oversight on the part of the designer has become more likely, and costlier to correct.

Signals that propagate too slowly through the circuit cause setup violations; signals that propagate too quickly through the circuit cause hold violations.

Setup or hold violations frustrate the logic of the circuit and prevent it from performing the job it was designed to do.

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