Co-processing acceleration method, apparatus, and system

Active Publication Date: 2013-06-13
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a computer system and related tools to reduce memory usage and increase processing speed. By using a public buffer card as a buffer for processing between nodes and co-processor cards, data does not need to be transferred through the main computer memory, avoiding memory usage. This reduces bandwidth limitations and increases the speed at which data is processed.

Problems solved by technology

However, the processing capability of a single computer is limited, and is likely to become a bottleneck of improving system performance in the foregoing large-scale computing scenarios, and this problem is effectively solved as a cluster system emerges.
By adopting such architecture in the prior art, all to-be-processed data has to be transferred through the memory of the computer node, which increase memory overheads, and due to the limits of factors such as the memory bandwidth and delay, a co-processing speed is not high.

Method used

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  • Co-processing acceleration method, apparatus, and system
  • Co-processing acceleration method, apparatus, and system
  • Co-processing acceleration method, apparatus, and system

Examples

Experimental program
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embodiment 2

[0069]An embodiment of the present invention provides a co-processing acceleration method, which is used to increase a speed of co-processing in a computer system. As shown in FIG. 3, the method includes:

[0070]S201: Receive at least one co-processing request message sent by a compute node in a computer system.

[0071]In an embodiment, each co-processing message carries address information of to-be-processed data (that is, to-be-processed data on which processing is requested by the by the compute node through the co-processing message) corresponding to the co-processing message.

[0072]Specifically, in the computer system, at least one compute node and at least one co-processor card exist. The co-processor card may aid the compute node in task processing, that is, co-processing. When the compute node needs aid of the co-processor card in task processing, the compute node sends a co-processing request message. In an embodiment, the co-processing request message may be a data packet inclu...

embodiment 3

[0109]The embodiment of the present invention provides a co-processing task management apparatus, configured to manage co-processing tasks in a computer system in a unified manner. As shown in FIG. 4, the co-processing task management apparatus includes:

[0110]A message receiving module 420 is configured to receive at least one co-processing request message sent by a compute node in the computer system, where the co-processing request message carries address information of to-be-processed data.

[0111]Specifically, in the computer system, if the compute node needs a co-processor card to process the to-be-processed data, the compute node sends a co-processing request message to the message receiving module 420. The message receiving module 420 receives the co-processing request message sent by the compute node. Content included in the co-processing request message are exactly the same as content of the co-processing request message described in S101 of Embodiment 1 of the present invent...

embodiment 4

[0132]as shown in FIG. 6, Embodiment 4 of the present invention provides a computer system, including:

[0133]a hard disk 101, a bus exchanger 102, a public buffer card 103, a co-processing task management apparatus 104, at least one compute node (for example, a compute node 105 in FIG. 6), and at least one co-processor card (for example, a co-processor card 112 in FIG. 6); where the co-processor card 112, the hard disk 101, and the public buffer card 103 are coupled in data connection to the bus exchanger 102, the bus exchanger 102 makes the co-processor card 112, the hard disk 101, and the public buffer card 103 be interconnected; the at least one compute node 105 is configured to send a co-processing request message, the co-processing request message carries address information of to-be-processed data, and the to-be-processed data is data on which processing is requested by the compute node 105.

[0134]The co-processing task management apparatus 104 is configured to: receive the co-p...

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Abstract

An embodiment of the present invention discloses a co-processing acceleration method, including: receiving a co-processing request message which is sent by a compute node in a computer system and carries address information of to-be-processed data; according to the co-processing request message, obtaining the to-be-processed data, and storing the to-be-processed data in a public buffer card; and allocating the to-be-processed data stored in the public buffer card to an idle co-processor card in the computer system for processing. An added public buffer card is used as a public data buffer channel between a hard disk and each co-processor card of a computer system, and to-be-processed data does not need to be transferred by a memory of the compute node, which avoids overheads of the data in transmission through the memory of the compute node, and thereby breaks through a bottleneck of memory delay and bandwidth, and increases a co-processing speed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of International Application No. PCT / CN2011 / 083770, filed on Dec. 9, 2011, which are hereby incorporated by reference in their entireties.FIELD OF THE INVENTION[0002]The present invention relates to the computer field, and in particular, to a co-processing acceleration method, an apparatus, and a system.BACKGROUND OF THE INVENTION[0003]With the development of computer technologies, computers are applied in increasingly wider fields. In addition to common computer office applications in everyday life, the computers are also applied in some very complex fields, such as large-scale scientific computing and massive data processing, which usually have higher requirements on the processing capability of the computers. However, the processing capability of a single computer is limited, and is likely to become a bottleneck of improving system performance in the foregoing large-scale computing scenarios, and this...

Claims

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Application Information

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IPC IPC(8): G06F13/36
CPCG06F15/167G06F9/3881G06F9/544G06F9/505
Inventor ZHANG, XIAOFENGFANG, FANQIN, LING
Owner HUAWEI TECH CO LTD
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