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Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure

a technology of automated test equipment and test flow, applied in the field of automation test equipment, can solve problems such as process defects, and achieve the effect of reducing the time to detect any defects

Inactive Publication Date: 2011-11-24
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0005]The present invention describes a system and method for optimizing a test flow within an ATE station to minimize the time to detect any defects or failures on a semiconductor chip or a wafer.

Problems solved by technology

Defects in the process may occur due to several operational, mechanical or chemical control errors, or due to environmental uncertainty, e.g., contamination during the process.

Method used

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  • Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure
  • Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure
  • Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure

Examples

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Embodiment Construction

[0016]According to one embodiment of the present invention, a test floor may include a plurality of ATE stations (i.e., individual testers). An ATE station includes at least one test flow, which is defined by a test program (e.g., a test program 340 in FIG. 3). A test flow comprises a plurality of test blocks. The test flow lists the plurality of tests or test blocks in a sequence according to which they are run. A test block includes one or more individual tests, e.g., tests measuring leakage current and threshold voltage. The test block refers to a group of individual tests that could not or should not be separated. The individual tests in the test block need to be run together in a specific sequence. The individual testers may perform the individual tests.

[0017]According to one embodiment of the present invention, an ATE station receives as input one or more of: a test process structure, a test process constraint and a stopping criterion. The test process structure includes, but ...

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Abstract

The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

Description

BACKGROUND[0001]The present invention generally relates to an ATE (Automated Test Equipment). More particularly, the present invention relates to optimizing a test flow within an ATE.[0002]An ATE station refers to any automated device that is used to test printed circuit boards, integrated circuits or any other electronic components. Agilent® Medalist i1000D, Agilent® Medalist i3070, Teradyne® Catalyst, Teradyne® Tiger, Teradyne® FLEX and Teradyne® UltraFLEX are examples of an ATE station.[0003]A semiconductor manufacturing process requires a sequence of complex operations on each wafer to create multi-layered physical and electrical structures that form a desired very large scale integrated circuitry (VLSI). Defects in the process may occur due to several operational, mechanical or chemical control errors, or due to environmental uncertainty, e.g., contamination during the process. After manufacturing of semiconductor chips on each wafer is complete, a set of comprehensive electric...

Claims

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Application Information

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IPC IPC(8): G06F19/00G01R31/26
CPCG06F11/27G01R31/2894
Inventor FAN, WEIHALIM, NAGUIJOHNSON, MARK C.PARTHASARATHY, SRINIVASANTURAGA, DEEPAK S.VERSCHEURE, OLIVIER
Owner IBM CORP
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