Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.

Description

[0001]CROSS-REFERENCE TO RELATED PATENT APPLICATIONS[0002]This application is a continuation of application Ser. No. 11 / 987,854, filed Dec. 5, 2007, now pending, and based on Japanese Patent Application No. 2006-331618, filed Dec. 8, 2006, by Hiroshi Furuta, which is incorporated herein by reference in its entirety. This application claims only subject matter disclosed in the parent application and therefore presents no new matter.BACKGROUND OF THE INVENTION[0003]1. Field of the Invention[0004]The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a decoupling capacitor (on chip capacitor).[0005]2. Description of Related Art[0006]With increasing number of devices and higher speed of LSI (Large Scale Integration), the problem of power supply noise is becoming serious. As a countermeasure against this power supply noise, the method of connecting a power source line and a ground line by a decoupli...

AI Technical Summary

Benefits of technology

[0019]In one embodiment, a semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor. By having a large-shaped capacitance device near external terminals where more current flows, it is possible to improve ESD robustness of the capacitor itself. Furthermore, mounting a plurality of capacitors in different shapes enables to correspond to noise of various frequencies.

[0020]The present invention is able to provide a semiconductor integrated circuit device having a decoupling capacitor capable of achieving both the noise countermeasure of a circuit and ESD protection.

Problems solved by technology

With increasing number of devices and higher speed of LSI (Large Scale Integration), the problem of power supply noise is becoming serious.

In recent years, the countermeasure against ESD for the decoupling capacitor itself is posing a serious problem due to a thinner gate insulating film.

A change in the circuit size and capacity to mount may cause insufficient noise reduction effect by the decoupling capacitor.

By increasing number of devices and higher speed of LSI, diversification of power supply noise and high frequency noise in each functional block inside a chip are becoming a problem.

However, as generated noises are different for each circuit, it cannot be supported by one resonant circuit and a filter circuit.

Moreover, Ogawa does not support the types of noises (frequency characteristics of a capacitor).

However, such consideration has not been made for the arrangement of conventional decoupling capacitors.

Furthermore, by a thinner insulating film of a decoupling capacitor (gate insulating film in case of a MOS capacitance), ESD robustness of the decoupling capacitor itself has become a problem.

However, both ESD robustness of a decoupling capacitor and noise reduction have not simultaneously been taken into consideration.

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