Fast read port for register file

Abstract

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional of pending U.S. patent application Ser. No. 11 / 130,929; filed May 17, 2005.TECHNICAL FIELD [0002] The invention relates to memory systems and read operations. More specifically, the invention is a single-ended read port and sense amplifier with integral precharge capability. BACKGROUND ART [0003] A static memory cell constructed from six transistors is commonly applied in memory designs to fulfill requirements for short access cycle times, high-frequency data rates, low power consumption, and excellent immunity from extreme environmental conditions. [0004] With reference to FIG. 1A a six transistor (6-T) cell latches digital data in a memory cell latch loop formed by a pair of cross-coupled inverters in a prior art static memory cell diagram 101. A first complementary inverter is constructed from a first PMOS transistor 115 and a first NMOS transistor 125. A second complementary inverter is constructed from a second ...

AI Technical Summary

Benefits of technology

[0010] Separate read and write ports in a memory system allow simultaneous access to a memory cell array in read and write operations. A single cycle operation of a central processing unit coupled to a memory cell array depends on a memory access capability incorporating simultaneous read and write operations. A pair of pull-down transistor stacks coupled to a memory cell latch loop allow a selected single pull-down stack of the pair to toggle the memory cell latch loop to a desired data content without any requirement for a precharge scheme. An additional single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading and minimal likelihood of upsetting a memory cell data content in a read operation. A sense amplifier provides a mid-supply-level precharge capability produced by a feedback device within a front-end inversion stage. The front-end inversion stage, cascaded with a second inversion stage, provides a rapid read response. A memory cell of the present invention may be used for a register file, a specialized SRAM, or a generic SRAM.

Problems solved by technology

The pullup stack replication increases an overall memory array size and complexity.

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