Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same

Abstract

Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to an integrated circuit device including a scan test circuit, a method of testing the integrated circuit device, a database for use in design of the integrated circuit device and a method of designing the integrated circuit device. [0002] An integrated circuit device, such as a system LSI, including a large number of circuits as well as a scan test circuit for testing these circuits is conventionally known. [0003]FIG. 13 is a perspective view for illustrating a state of designing an integrated circuit device in which data of circuits to be designed are taken out from a database. Data of the respective circuits are registered in the database as a core 1, a core 2, a core 3 and a core 4, which are taken out from the database to be appropriately arranged in the integrated circuit device. As the data of these cores, data previously used may be reused or new data may be created. [0004] Although not shown in FIG. 13, some i...

AI Technical Summary

Benefits of technology

"The invention aims to reduce peak power consumption during a scan test of an integrated circuit device. This is achieved by providing means for dispersing the operation timing of circuit elements in the device, while preventing changes in the internal state of the logic circuits during the shift operation of the scan test. The first integrated circuit device of the invention includes multiple logic circuits and flip-flop circuits connected in a scan test circuit. A scan test is conducted by repeating a holding operation for fixing an output signal from each flip-flop circuit, a shift operation for sending a scan test signal and a data signal to the logic circuits, a hold releasing operation for releasing the output signal after the shift operation, and a capture operation for capturing the output signal. The second integrated circuit device of the invention includes first and second circuits, a clock supply part for supplying a clock signal to the first and second circuits, a clock inverting part for inverting the clock signal, and an output switching circuit for selectively outputting the inverted clock signal or the original clock signal. The methods described in the patent text can be used to suppress peak power consumption during the scan test and hold the output signal in a fixed state during the shift operation."

Problems solved by technology

This is because, when the tester is used for a long period of time, the cost of the integrated circuit device ultimately becomes high due to high running cost of the tester.

When a large number of cores are operated in a short period of time as in the aforementioned scan test of the integrated circuit device, however, the momentary power consumption (peak power consumption) during the test can be very large.

Particularly, since a large number of and a variety of circuits are recently packed in one chip of an integrated circuit device such as a system LSI, the peak power consumption is estimated to be extremely large.

Although power supply is generally designed with respect to power consumption during general use of a device, the power supply design does not take the increase of peak power consumption during the test into consideration.

In general use, there is substantially no chance that all the circuits included in an integrated circuit device are simultaneously operated, and hence, the peak power consumption during general use is not very large.

As a result, an integrated circuit device designed without considering the peak power consumption during the test cannot be normally operated in the scan test or can be damaged by the test.

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