Semiconductor device including bit line formed using damascene technique and method of fabricating the same

Abstract

A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

Description

CROSS REFERENCES TO RELATED APPLICATIONS [0001] This is a divisional application of U.S. application Ser. No. 10 / 703,328 filed on Nov. 7, 2003, the disclosure of which is herein incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device having conductive layers, such as bit lines, which are closely formed to be parallel, and a method of fabricating the same. [0004] 2. Description of the Related Art [0005] As the integration density of semiconductor memory devices, such as DRAMs, increases, more attention is being paid to methods of minimizing chip size. In recent years, DRAM cells having a design rule of 0.11 μm or less have been developed. However, as the design rule and chip size of DRAMs decrease, overcoming restrictions of photolithographic processes used to form...

AI Technical Summary

Benefits of technology

[0009] An aspect of the present invention is to provide a method of fabricating a semiconductor device, in which, despite the reduced design rule, bit line patterns can be easily formed and the process margin can be sufficiently secured.

[0010] Another aspect of the present invention is to provide a semiconductor device including a bit line, in which the misalignment margin between the bit line and a storage node contact hole is increased.

[0015] According to various exemplary embodiments of the present invention, formation of a bit line employs not a photolithographic process but a damascene technique. Thus, even a bit line having the reduced design rule can be easily formed. Also, misalignment between a bit line and a lower conductive element (e.g., a bit line contact plug), which occurs due to the reduced design rule, can be minimized. Further, because the dimension of a bit line opening is adjusted by controlling the width of the spacers, a bit line conductive layer can be formed to below the photolithographic limit. In addition, as it is not required to fill a gap between bit lines with a gap fill insulating layer, a void does not occur in the gap fill insulating layer. The present invention is not limited to bit lines but can also be applied to adjacently formed conductive layers, such as, for example, various interconnections or gate lines.

Problems solved by technology

However, as the design rule and chip size of DRAMs decrease, overcoming restrictions of photolithographic processes used to form the DRAMs and securing a sufficient process margin become more complicated.

However, the foregoing conventional method using photolithographic exposure equipment cannot obtain finer bit line patterns.

Thus, sufficiently reducing the cell size becomes difficult.

Also, the misalignment margin between a bit line and a bit line contact plug may be reduced, thus causing problems such as leakage.

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