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Apparatus, system, and method for reducing integrated circuit peeling

a technology of integrated circuit and peeling, applied in the field of apparatus, system and method for reducing integrated circuit peeling, can solve the problems of cross contamination, serious problems to the functionality of the integrated circuit and purity of the processing environment, and often collect unwanted film around the perimeter of the wafer, so as to effectively remove unwanted film, improve etching controllability and efficiency, and eliminate the effect of integrated circuit peeling

Inactive Publication Date: 2006-08-03
LSI CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0013] The solvent used to clean the perimeter of the wafer may comprise a solution containing water such as water and hydrogen fluoride. The apparatus substantially eliminates integrated circuit peeling due to the chemical affinity between the solvent and solventphilic layer—thus enabling the solvent to remain on the solventphilic layer longer and more effectively remove the unwanted film.
[0014] The apparatus may also include an etching boundary. In one embodiment, the etching boundary is formed by conducting a dry edge etch process on one or more integrated circuit layers. In certain embodiments, the etching boundary is at least 0.9 micrometers in height. The height of the etching boundary may improve etching controllability and efficiency by introducing a barrier to impede the migration of the solvent used in the etching process.
[0018] The disclosed method, apparatus, and system substantially eliminate integrated circuit peeling due to the chemical affinity between a selected solvent and a solventphilic layer that enables the solvent to remain on the solventphilic layer longer, and thereby more effectively remove unwanted film. These features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

Problems solved by technology

As additional layers are added during preparation of the integrated circuit, unwanted film often collects around the perimeter of the wafer.
Unless removed, the unwanted film may pose serious problems to the functionality of the integrated circuit and purity of the processing environment.
For example, the unwanted film may later peel and be transferred to another sensitive electrical device or be scattered around, resulting in cross contamination, wherein the peeled-off fragments contaminate the processing environments of other processes.
Though dry edge etching allows for controllable etching, it is also costly and time consuming.
Furthermore, dry edge etching may produce defects in the integrated circuit caused by particles left over from the photo mask step.
Though wet edge etching is cheaper and faster than dry edge etching, it does not allow for controlled etching, and therefore, often results in over or under etching.
Over etching may destroy the functionality of the integrated circuit in that vital portions of the device may be removed along with the unwanted film.
If under etching occurs, not all the unwanted film is removed and peeling remains a risk.
In short, though wet edge etching is beneficial because wet edge etching is more efficient than dry edge etching, wet edge etching is also problematic because wet edge etching is difficult to control.

Method used

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Embodiment Construction

[0028] Reference throughout this specification to “one embodiment,”“an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,”“in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0029] Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structur...

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Abstract

An apparatus, system, and method are disclosed for reducing integrated circuit peeling. This invention reduces integrated circuit peeling by providing a wafer with a solventphilic layer and removing unwanted film using a solvent that is philic to the solventphilic layer. In one embodiment, a boundary is provided to reduce the rotation speed precision required to reach the desired etching distance. In certain embodiments, a wet edge etching process is used to remove unwanted film from the perimeter of the solventphilic layer. In certain embodiments, the solventphilic layer comprises a hydrophilic layer such as silicon nitride, and the solvent comprises a solution of water and hydrogen fluoride.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention relates generally to devices, methods, and systems for preparing integrated circuits. Specifically, the invention relates to devices, methods, and systems for reducing integrated circuit peeling by removing unwanted film. [0003] 2. Description of the Related Art [0004] Integrated circuits are pervasive among electronic devices including computers, audio and video equipment, appliances, and industrial control equipment. The pervasive utilization of integrated circuits is largely due to their small size and ability to process data. In the foreseeable future, integrated circuits will be introduced into additional electronic devices due to their ever-increasing processing capacity, shrinking size, and decreasing price. [0005] Integrated circuits are often fabricated on a wafer of semiconductive material whereon layers of conductive materials are placed having selective properties. As additional layers are ...

Claims

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Application Information

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IPC IPC(8): H01L23/58C23F1/00H01L21/461
CPCH01L21/02087H01L21/31111H01L21/6715H01L2224/274
Inventor SATO, NOBUYOSHI
Owner LSI CORPORATION
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