Isolation structures for imposing stress patterns

Abstract

A substrate under tension and / or compression improves performance of devices fabricated therein. Tension and / or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

Description

CROSS REFERENCES TO RELATED APPLICATIONS [0001] U.S. patent application Ser. No. 10 / ______, entitled “Stress Inducing Spacers” filed concurrently herewith is assigned to the same assignee hereof and contains subject matter related, in certain respect, to the subject matter of the present application. The above-identified patent application is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Technical Field of the Invention [0003] This invention pertains to inventive methods of manufacturing a semiconductor device for improving device performance, and to the resulting unique high-performance device structure. In particular, this invention has improved charge mobility in FET devices by structurally imposing tensile and compression forces in a device substrate during device fabrication. [0004] Within the field of semiconductor device design, it is known that mechanical stresses within the device substrate can modulate device performance. Individual stress tensor ...

AI Technical Summary

Benefits of technology

This patent describes a method and structure for improving the performance of NFET and PFET devices by applying biaxial tensile and compressive stresses simultaneously. The method can be used to fabricate both devices on a common substrate, and the structures are unique for each device. The invention provides enhanced performance relative to uniaxial stresses and can be integrated into existing manufacturing processes. The invention also includes a trench isolation structure for both devices, which applies different types of mechanical stress on each device. The invention also includes source and drain regions with stress inducing isolation material to enhance performance. The technical effects of this invention include improved device performance and more efficient use of substrate space.

Problems solved by technology

Prior known solutions and methods using mechanical stress for device performance enhancement could not improve both NFETs and PFETs simultaneously.

Moreover, prior solutions do not address the feasibility of any kind of device structures or methods of fabricating them.

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