Formation of self-aligned contact plugs

Abstract

Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation layer after the contact region is protected, which is followed by the formation of the self-aligned contact structures. A second method provides process steps to create an inner dielectric isolation layer after the self-aligned contact structures are formed.

Description

FIELD OF THE INVENTION [0001] This invention relates to semiconductor fabrication processing and, more particularly, to methods for forming self-aligned contact plugs for semiconductor devices, such as dynamic random access memories (DRAMs). BACKGROUND OF THE INVENTION [0002] The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. One important area in semiconductor fabrication is forming the interconnecting structure within the integrated circuit and particularly connection between a transistor and other devices. [0003] As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. In semiconductor devices it may be advantageous to build contact plugs for interlayer connections having high aspect ratio structures, as circuit density will be enhanced. In that light, the ability to precisely ali...

AI Technical Summary

Problems solved by technology

Removing doped oxide relative to un-doped oxide can be more difficult than removing an oxide relative to nitrite.

As such, if too high of a selectivity is used the contact opening can become blocked with the polymer layer.

Balancing the thickness of the polymer layer, etch selectivity, contact width and the thickness of the sidewall spacer is challenging.

Prior etch processes have been limited to a selectivity of oxide to nitride in the range of less than 40:1.

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