Method for manufacturing semiconductor element

Abstract

The invention proposes a method for manufacturing a semiconductor element which has shallow, high-dopant concentration source / drain regions. The manufacturing method is provided that, a gate electrode is formed on a substrate, and the source / drain regions of the substrate are transformed into an amorphous state by implanting ions. A co-implantation process is performed to implant ions in the source / drain regions. Thereafter, one or more implants may be performed to form the LDD and source / drain regions and the substrate is recrystallized. The amorphous regions and the co-implantation regions effectively confine or reduce the diffusion of the ions used to form the LDD and source / drain regions.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to source / drain regions of complementary metal oxide semiconductor (CMOS) transistors. Background technique [0002] CMOS technology is the mainstream semiconductor technology for manufacturing Ultra Large Scale Integration (ULSI) today. Over the past few decades, the scaling of semiconductor structures has dramatically increased the speed, performance, circuit density, and cost per computing unit of semiconductor chips. However, as the size of CMOS components continues to decrease, semiconductor technology faces greater challenges. [0003] As an example, when the length of the gate electrode of a CMOS transistor becomes smaller, especially when the gate length is less than 30 nm, the interaction between the source and drain regions and the channel increases, and the source and drain regions interact with the channel. potential to increase with the influence of the gate di...

AI Technical Summary

Problems solved by technology

However, the aforementioned shrinking source / drain region size tends to increase source / drain resistance and worsen its polysilicon gate depletion.

Therefore, shrinking the source / drain junction will reduce the drive current of the PMOS device.

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