Energy recovery latch circuit with set and reset function
A latch circuit and energy recovery technology, applied in logic circuits, electrical components, pulse technology, etc., can solve the problems of no setting/resetting of output signals, complex circuit structure, and limiting the application range of adiabatic circuits.
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[0035] The present invention is further illustrated below by an embodiment.
[0036] refer to Figure 5 As shown, it is a latch circuit structure with a set / reset function based on a 2n-2n2p2d complementary cross-coupled energy recovery circuit structure, including:
[0037] Two sets of transmission gate structures (MP1 and MN1, MP2 and MN2) connected in series to control the on / off of the power clock (PC signal) by the set / reset signal; the gates of the PMOS transistors are respectively connected to the set / reset signal S, R, the source of MP1 is connected to the power clock (PC signal), the drain of MP1 is connected to the source of MP2, and the drain of MP2 is connected to node C; the gates of the NMOS transistors are respectively connected to the set / reset complementary signals Sb, Rb, the drain of MN1 is connected to the power clock (PC signal), the source of MN1 is connected to the drain of MN2, and the source of MN2 is connected to the C node;
[0038] A pair of PMOS ...
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