Scan test design method, scan test circuit, scan test circuit insertion cad program, large-scale integrated circuit, and mobile digital device

Abstract

In designing a scan test circuit, in the final stage element (101f) unit of a clock tree (T), a plurality of flip-flop circuits (102a to 102a, 102b to 102b, 102c to 102c, ...) driven by the final stage element (101f) are connected in series, thereby constituting a sub-scan chain. Moreover, sub-scan chains having a minimum relative stage difference (i.e., one stage difference) of the number of delay elements from the clock supply point (S) of the clock tree (T) are connected to one another. Furthermore, the sub-scan chains are connected to one another in such a manner that data is shifted from a flip-flop circuit having a large clock delay to a flip-flop circuit having a small clock delay. Accordingly, the number of delay elements inserted into the data line of the shift register as the hold time guarantee in the shift operation of the scan shift register is reduced, thereby reducing the power consumption.

Description

technical field [0001] The present invention relates to a large-scale integrated circuit design method, a large-scale integrated circuit test circuit, and a large-scale integrated circuit design computer-aided design program. The design assurance and control of the hold time of operation is a test simplification design technique that accompanies the increase of circuit area, the increase of power consumption and the increase of leakage current with the insertion of hold guarantee delay elements. Background technique [0002] With regard to test simplification design, the case of scan test design is by far the most general. according to Figure 5 Describe the scan test design. [0003] exist Figure 5 Among them, after designing the register transfer level (RTL), the register transfer level file 501 is used as input data to carry out logic synthesis computer-aided design program 502 to generate a gate level netlist (netlist) 503 . First, by using the scan test circuit inser...

AI Technical Summary

Problems solved by technology

Therefore, there are problems of an increase in circuit area, an increase in power consumption, and an increase in leakage current when many delay elements are in standby.

[0008] As above figure 2 As in the example shown, in the conventional circuit that interconnects FF circuits between different clock trees, if a circuit that is easily affected by interference such as crosstalk (crosstalk) and voltage drop (IR drop) is used In the design of semiconductor micro-processes, the delay time of the clock tree part is affected by the above-mentioned interference and voltage drop, and more margin is required when transmitting shift data, so the delay element inserted in the scan shift circuit part further increase in the number of

The further increase in the number of delay elements caused by the above-mentioned test simplification design will further increase the circuit area of ​​the large-scale integrated circuit, and even lead to an increase in power consumption and a significant increase in the leakage current of many delay elements in standby

Images