Compound dynamic preset number representation and algorithm, and its processor structure

Abstract

This invention offers a new fixed-point number representation to represent the digital data after it is numerically conversed. This new representation includes two parts. The first part is that it setthe reserved number of least significant bits in the digital data as a dynamic dislocation value. This value represents the shifted digit capacity in numeric conversion. The other part is that it corresponds all the bits except the dynamic dislocation value to the partial bits of the digital data before numerical conversion. The partial bits includes at least a most important bit containing the numeric information.

Description

technical field [0001] The invention provides a new type of fixed-point number arithmetic algorithm and a related digital signal processor, especially a compound dynamic fixed-point number representation method that can convert digital data between a fixed-point number representation method and a composite dynamic fixed-point number representation method. Point algorithm (Joint Adaptive Fixed-Point Arithmetic) and related digital signal processors. Background technique [0002] In the past ten years, with the rapid development of VLSI technology and computer technology, and the urgent need for real-time digital signal processing, the electronic information industry has successively launched various functional types of digital signal processors (Digital Signal Processor, DSP). These digital signal processors generally have the advantages of good flexibility, high precision, and powerful functions. The application fields of digital signal processors are very wide. However, in...

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Problems solved by technology

The main target market for many fixed-point digital signal processors today is embedded application systems, where the memory capacity needs to be smaller than usual, and figure 1 When the fixed-point digital signal processor 10 is used in conjunction with such a smaller memory, when performing relevant fixed-point operations, it is forced to have a resolution limitation (resolution limitation), and Often there will be a quantization error (QuantizationError) occurs

read on figure 1 , figure 1 After the two n-bit digital data are multiplied by the multiplication circuit 16, the product is 2n-bit digital data, and after a series of processing, if the second shifting device 24 will have the 2n-bit digital representation of the fixed-point number representation When the data is converted into n-bit digital data to be stored in an n-bit memory, in the case where the 2n-bit digital data is in decimal form, the higher n bits of the 2n-bit digital data must be taken, and The lower n bits are discarded, and in the process of discarding the digits, it is easy to cause an error between the converted n-bit digital data and the original 2n-bit digital data

For example, the 48 bits of a (binary notation) in hexadecimal notation are: 0x004444ffffff, if the lower 24 bits are used to convert to 24-bit digital data, it becomes 0x004444, and then the point calculation is often specified The value 0x004444000000 restored by the method is obviously different from the original value, which causes the above-mentioned quantization error

This quantization error may cause discontinuity, distortion, and other undesirable effects on the size of the digital signal, which has become a limitation on the performance of conventional fixed-point digital signal processors 10

If you want to increase the number of digits of the digital signal processor, or use a floating-point digital signal processor to improve the quantization error, the hardware cost will increase significantly.

In addition, the method of modifying the program code of the fixed-point digital signal processor to reduce the quantization error will increase the program complexity and occupy more computing performance of the digital signal processor

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