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Process for controlling denuded zone depth in an ideal oxygen precipitating silicon wafer

A technology of oxygen precipitation and silicon wafers, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve the problems of high interstitial oxygen concentration and reducing the resistivity of silicon wafer device layers.

Inactive Publication Date: 2005-06-08
MEMC ELECTONIC MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, once the clean zone becomes too deep or too thick, there is a possibility of elevated interstitial oxygen concentration in the center of this zone (interstitial oxygen near the surface and bulk of the wafer has enough time to diffuse to where they are consumed ) will be high enough that thermal donors will form during device fabrication, thus reducing the resistivity in the silicon device layer

Method used

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  • Process for controlling denuded zone depth in an ideal oxygen precipitating silicon wafer
  • Process for controlling denuded zone depth in an ideal oxygen precipitating silicon wafer
  • Process for controlling denuded zone depth in an ideal oxygen precipitating silicon wafer

Examples

Experimental program
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Effect test

example 1

[0071] Example 1 and figure 2 Indicates the gettering capacity of an ideal deposited silicon wafer in a range of oxygen concentrations. In the first set of experiments, an ideal precipitated silicon wafer with an oxygen concentration of 13PPMA was heat-treated at 1200°C in step S 1 Formation followed by bulk precipitation of oxygen grows at a temperature of 950° C. in the range of 30-180 minutes. Repeat step S with heat treatment temperature of 1225°C and 1250°C 1 . In the second and third sets of experiments, the first set of experiments was repeated on ideal precipitated silicon wafers with 11.5 PPMA and 9.5 PPMA oxygen precipitation concentrations, respectively. The gettering ability was measured by contaminating the rear surface of the silicon wafer with nickel. figure 2 The arrow in indicates the start of complete aspiration. The data show that for ideally precipitated silicon wafers over a range of oxygen concentrations, even at low oxygen concentrations, bulk dep...

example 2

[0073] Four silicon wafers were cut from two segments of high-resistivity CZ crystal. Three silicon wafers were ideally heat-treated for precipitated silicon wafers at 1235°C, 1250°C and 1275°C respectively. The fourth wafer is a controller, without ideal thermal treatment of precipitated wafers. Each wafer was then quartered and subjected to the following secondary annealing:

[0074] Wafer GG, quarter 1 (GGQ1): 4 hours at 800°C, followed by 16 hours at 1000°C;

[0075] Wafer GG, quarter 2 (GGQ2): 8 hours at 800°C, followed by 16 hours at 1000°C;

[0076] Wafer GG, quarter 3 (GGQ3): ramp from 800°C to 1000°C at a rate of 1°C / min, followed by 1 hour at 1000°C; and

[0077] Wafer GG, quarter 4 (GGQ4): Ramp from 800°C to 1000°C at a rate of 2°C / min, followed by 1 hour at 1000°C.

[0078] silicon wafer

[0079] The control wafers did not receive ideal precipitated wafer processing, so the precipitate density after thermal cycles was derived from pre-existing precipita...

example 3

[0081] silicon wafer

[0082] The 800°C-1000°C ramp anneal (Q3 and Q4) is not very effective at growing the precipitates formed during the ideal precipitated wafer process, thereby removing little interstitial oxygen in solution. In contrast, the two-step 800°C and 1000°C anneals (Q1 and Q2) were much more effective at growing the precipitates formed during the ideal precipitated wafer process and removing interstitial oxygen in solution. Additionally, the 8 hr / 800°C anneal is more effective at removing interstitial oxygen than the 4 hr / 800°C anneal. Moreover, the final O after the two-step annealing i It decreases with the increase of the high temperature annealing temperature of the ideal precipitated silicon wafer. Finally, the data show that the final O i With initial O i Varies, the higher the initial O i This provides greater supersaturation which results in a greater removal of interstitial oxygen from solution during the secondary anneal.

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Abstract

The present invention is directed to a single crystal Czochralski silicon wafer having a non-uniform distribution of lattice vacancies with peak concentration at a hypothetical In the bulk of the wafer between the central plane and a surface, such that after a heat treatment cycle in essentially any electronic device manufacturing process, the wafer forms oxygen precipitates in the bulk and a thin or shallow no-sedimentation zone.

Description

technical field [0001] The present invention generally relates to the preparation of a semiconductor material substrate, in particular a silicon wafer suitable for use in the manufacture of electronic components. More particularly, the present invention relates to a method for processing a silicon wafer to form therein a non-uniform distribution of lattice vacancies such that during the thermal treatment cycle of essentially any electronic device manufacturing process, the silicon wafer is Oxygen precipitates are formed in the middle, and a thin or shallow precipitation-free zone is formed near the surface. technical background [0002] Single crystal silicon, the raw material for most processes used in the manufacture of semiconductor electronic components, is usually produced by the so-called Czochralski process, in which a single crystal seed is dipped into molten silicon , and then grow by slow pulling. During the time it is contained in a quartz crucible, molten silic...

Claims

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Application Information

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IPC IPC(8): H01L21/322
CPCH01L21/3225H01L21/3226H01L21/324
Inventor J·L·利伯特M·J·宾斯R·J·法尔斯特
Owner MEMC ELECTONIC MATERIALS INC
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