Implementing method of parallel frame locator for optical synchronous digital transmission system
A technology of optical synchronous digital transmission system, which is applied in the field of frame positioning, can solve the problems of difficulty in circuit implementation and high production and processing costs, and achieve the effects of simple circuit implementation, reduced power consumption, and cost savings
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[0036] For the convenience of description below, assume that K is 1, and the frame alignment mode is 2A12A2 (0xF6F62828), that is, if two A1 bytes are found and then two A2 bytes are found, it is considered that the frame header has been searched. The functional block diagram of the parallel frame locator is shown in image 3 shown.
[0037] Latch the 8-bit parallel input data of 6 parallel clock beats to reg0[7:0]~reg5[7:0], and perform 8 parallel 32-bit comparisons at the same time, respectively:
[0038] Comparator 1: reg1[7:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and frame alignment mode
[0039] Comparator 2: reg0[7]+reg1[6:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and frame alignment mode
[0040] Comparator 3: reg0[7:6]+reg1[5:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and frame alignment mode
[0041] Comparator 4: reg0[7:5]+regl[4:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and frame alignment mode
[0042] Comparator 5: reg0[7:4]+reg1[3:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and frame alignment mode
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