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Method and device for correcting internal call or return stack in microprocessor

A microprocessor and stack technology, applied in machine execution devices, electrical digital data processing, instruments, etc., can solve problems such as microprocessors that cannot effectively use branch instruction misprediction, and achieve the effect of reducing the occurrence of air bubbles

Active Publication Date: 2004-12-29
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the device described in this patent can only be used in microprocessors in which a single stage of the pipeline can detect a branch instruction misprediction, and cannot be effectively applied to multiple stages in the pipeline to execute and detect branches. instruction misprediction in microprocessors

Method used

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  • Method and device for correcting internal call or return stack in microprocessor
  • Method and device for correcting internal call or return stack in microprocessor
  • Method and device for correcting internal call or return stack in microprocessor

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Embodiment Construction

[0053] Please refer to figure 1 , which is a schematic block diagram of a pipelined microprocessor 100 of the present invention. In a preferred embodiment, the microprocessor 100 such as figure 1 Twelve strata are included as shown.

[0054] The microprocessor 100 includes an I level 102 (or called an instruction fetch level 102). The I-level 102 can provide a fetch address to an instruction cache to fetch instructions for execution by the microprocessor 100 . If the fetched address misses in the instruction cache, the I-level 102 fetches the missing cache line from a main memory coupled to the microprocessor 100 . In a preferred embodiment, the I-level 102 includes a branch target address cache. By fetching addresses from the instruction cache, such a branch target address cache may be stored along an instruction cache within the I-level 102. Pick. In addition, the branch target address cache can store target addresses of previously executed branch instructions, as well ...

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Abstract

The present invention discloses one call / return stack (CRS) updating device in pipeline microprocessor. Whenever the microprocessor updates CRS based on one call / return command, it also stores the updating information in the first updating stack. The microprocessor includes two different stages for detecting null event. Once the call / return command passes through the first detection stage, the relevant information will move from the first updating stack to the second updating stack. When some null event is detected in the upper detection stage, only the updating information in the first stack may be used in updating CRS. However, if some null event is detected in the lower detection stage, the updating information in both the first and the second stack may be used in updating CRS.

Description

technical field [0001] The invention relates to the field of a call or return stack in a microprocessor, in particular to a method and device for maintaining consistency between a call or return stack and main memory. Background technique [0002] A microprocessor is a digital device that executes the instructions specified by a computer system. Modern microprocessors often use an internal call or return stack to reduce the occurrence of pipeline bubbles caused by lengthy memory accesses associated with call and return instructions. [0003] The call instruction includes an instruction for changing the program flow to a subroutine, wherein the address of the subroutine is specified by the call instruction. When a call instruction is executed, the return address (i.e., the address of the instruction following the call instruction) will be pushed into a stack in main memory specified by a stack pointer register in the microprocessor, and the The address of the subroutine wil...

Claims

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Application Information

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IPC IPC(8): G06F9/38G06F9/42
Inventor 汤玛斯·C·麦当劳
Owner IP FIRST
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