Non-synchronous first in first out controller using biedge sampling processing control signal

Abstract

An asynchronous FIFO controller using dual-edge sampling to process control signal is composed of a leading edge processing module for using the leading edg eof clock signal as latch time to latch the first external control signal and ata, which along with the second external control signal and data from the falling edge processing module are used to output the third control signal and data, a falling edge processing module for using the falling edge of clock signal as latch time to latch the first external control signal and data, which along with the fourth external control signal and data from leading edge processing module are used to output the fifth control signal and data, an integrated processing module for outputting the sixth control signal and data, and memory for storing the sixth control signal and data.

Description

technical field [0001] The invention belongs to a first-in-first-out (FIFO) controller, in particular to an asynchronous first-in-first-out (FIFO) controller using double-edge sampling to process control signals. technical background [0002] In the existing first-in-first-out (FIFO) controller, because the latch register (flip-flop) is sampled either on the rising edge or on the falling edge, sampling with both edges of the clock is equivalent to sampling data with two different clocks. Since the data is not sampled with the same clock signal, the data cannot be directly put into the FIFO controller according to the external signal, and an additional level of buffering is required, and then the data in the clock sampling buffer of at least an external clock signal is used. But this kind of processing first requires an additional internal clock signal twice the external clock, and secondly, because the clock signal has nothing to do with the input double data rate (DDR) cloc...

AI Technical Summary

Problems solved by technology

[0003] In order to solve the problem related to the setup time or hold time of sampling external data through the internal clock, it also makes it unnecessary to generate additional clock sampling data when the operating frequency is relatively low in the circuit. The purpose of the present invention is to directly use The relationship between the interface clock and data can safely and stably sample data, and the whole device only needs one working frequency, and the structure is simpler

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