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Method for testing interconnected bus of external components

A technology of peripheral component interconnection and testing method, which is applied in the direction of detecting faulty computer hardware, instruments, electrical digital data processing, etc., can solve problems such as insufficient coverage, limited system resources, and inability to test PCI bus performance, etc., to improve High test efficiency and resource coverage

Inactive Publication Date: 2004-07-28
INVENTEC CORP
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  • Summary
  • Abstract
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Problems solved by technology

The tests on the PCI bus are all functional tests, and cannot test the performance of the PCI bus when transmitting data at high speed
Due to the variety of PCI devices, it is difficult to guarantee the test results of other PCI devices, and the system resources required by general PCI devices are limited, so the test coverage is not enough, and it is difficult to test the throughput of large data

Method used

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  • Method for testing interconnected bus of external components
  • Method for testing interconnected bus of external components
  • Method for testing interconnected bus of external components

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Embodiment Construction

[0033] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0034] The PCI bus is a processor-independent local bus designed to meet high-speed data transmission. It has two multiplexed address data paths, 32-bit and 64-bit. One side is connected to the processor and memory bus interface, and the other side is Peripheral expansion provides high-speed channels. In terms of structure, the PCI bus is a first-level bus inserted between the CPU and the original system bus. A bridge circuit is used to manage this layer and realize data transmission between the upper and lower interfaces. In the bridge circuit manager Provide signal buffering, so that the PCI bus can support up to 10 external devices, and the PCI bus also supports bus master technology, which allows smart devices to obtain bus control rights to speed up data transmission when needed.

[0035] For a test method for the peripheral component interconnect bus, see fig...

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Abstract

The present invention relates to a testing method of interconnection buss for peripheral components. It utilizes PCI test card to directly operate I / O and internal memory space of PCI bus map, firstly, the PCI test card is inserted into PCI slot, then according to the configuration information the parameters required for host access can be distributed for said PCI test card, then the parameters can be written into the PCI configuration space of PCI test card, according to said configuration space the port mapping mode of said PCI test card can be defined, the data can be written into 32-bit and 64-bit address respectively, finally, according to fetch result the test conclusion can be obtained.

Description

technical field [0001] The invention relates to a hardware testing method, in particular to a testing method for interconnecting buses of peripheral components. Background technique [0002] The PCI (Peripheral Component Interface) bus is an advanced high-performance 32 / 64-bit address data multiplexing local bus, which can support multiple sets of peripheral devices at the same time, and is not restricted by the processor. It provides a communication bridge between the device and high-speed peripheral devices, and improves the data throughput (up to 132MB / s at 32 bits), which is a popular bus in the PC field today. The PCI bus is an advanced computer bus emerging in the mid-1990s. With its high performance and high reliability, it has quickly become the mainstream bus of today's computers. [0003] At present, the method for testing the PCI bus is to insert a PCI device on the bus and test the PCI device. The tests on the PCI bus are all functional tests, and cannot test t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F13/20
Inventor 刘文涵宋建福赵骐
Owner INVENTEC CORP
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