Realising method for parallel cascade convolution code hardware decoder

A technology of hardware decoding and implementation methods, which is applied in the field of simplified implementation of error correction code decoding devices, can solve problems such as the limitation of decoder operation speed, and achieve the effects of low decoding time delay, advanced time, and reduced data throughput

Inactive Publication Date: 2002-11-06
INST OF TELECOMM TRANSMISSION MINIST OF INFORMATION IND +1
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Problems solved by technology

If an off-chip memory chip is used, the operation speed of the decoder will be limited

Method used

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  • Realising method for parallel cascade convolution code hardware decoder
  • Realising method for parallel cascade convolution code hardware decoder
  • Realising method for parallel cascade convolution code hardware decoder

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Experimental program
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Embodiment Construction

[0021] Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0022] attached figure 1 .A block diagram of the implementation of the maximum a posteriori probability decoding algorithm in the traditional logarithmic domain. Wherein 1 is the branch measurement unit BMC, 2 is the forward state measurement unit FSMC, 3 is the reverse state measurement unit RSMC, 4 is the logarithmic likelihood ratio calculation unit LLRC, 5 is the memory unit, the size of the memory and the The data length N is the same.

[0023] For the convenience of description, the following agreement is made: the original information bit part x in the data to be decoded k , the check information bit part y in the data to be decoded k , the log likelihood ratio output L k .

[0024] attached figure 2 . The realization block diagram that the present invention uses. Among them, 3_I and 3_II are two reverse state measurement units RSMC, and 6...

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Abstract

In order to meet the saving needs required by FAMC and RSMC to the storage, the invented device of the present invention exchanges the increasing use of logic resources with the throughput decreasingof storage data when the use of site programmable logic gate-array is realized. The specific method is to use two sets of RSMC and both of them are working at the same time, and the iteration is started from different initial time to select the correct data output part. Its superority is that the data throughput of storing unit in the course of decoding realization does not rely on quanitity N ofdata which waist for decoding but only depends on the value L which can satisfy the requirement, when L is bigger than 5 times of constrained length of the coder with member's convolution code.

Description

(1) Technical field: [0001] The invention belongs to the technical field of communication, and in particular relates to a simplified implementation of an error correction code decoding device. (two) background technology: [0002] Parallel concatenated convolutional code (Turbo code) is a new error control code proposed by Berrou et al. in France in 1993. In the additive Gaussian white noise channel, its error correction performance is close to the Shannon limit, which is better than the original Some error control codes have better error correction performance. The coding principle of the Turbo code is to connect two convolutional code encoders in parallel and use an interleaving unit to separate them. In terms of the overall effect, the structure of the encoder improves the distance distribution of the entire coding sequence, and its ability to correct bit errors, especially the ability to correct channel burst errors has been strengthened. [0003] The traditional decod...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/00H03M13/23
Inventor 卫国黄源良赵春明
Owner INST OF TELECOMM TRANSMISSION MINIST OF INFORMATION IND
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