Sampling time-clock generation circuit, data transmission control device and electronic equipment

Abstract

Provided are a sampling clock generation circuit and a data transfer control device make it possible to ensure a set-up time and the like during sampling, while maintaining a high frequency. A sampling clock generation circuit 10 comprises an edge detection circuit 70 detecting between which two edges an edge of data DIN data to be transferred in USB2.0 HS mode is located, the two edges are among edges of clocks CLK0 to CLK4 that have the same frequency but mutually different phases, and a clock selection circuit 72, which selects one of CLK0 to CLK4 based on this edge detection information and outputs the thus-selected clock as a sampling clock SCLK. When the set-up time of a D flip-flop of the edge detection circuit is TS, the hold time is TH, and the period of the clock is T, N is the number of a multi-phase clock is given by: N <=[T / (TS + TH)], (where [X] is the maximum integer that does not exceed X). The clock that has an edge that is shifted by a set number M from an edge of the data DIN is selected as SCLK.

Description

technical field [0001] The present invention relates to a sampling clock generation circuit, a data transfer control device and electronic equipment. Background technique [0002] In recent years, USB (Universal Serial Bus) has attracted attention as an interface standard for connecting personal computers and peripheral devices (electronic devices in a broad sense). The advantage of this USB is that peripheral devices such as mouse, keyboard and printer can be connected with connectors of the same specification. In the past, these devices were connected with connectors of different specifications. . [0003] On the other hand, compared with IEEE1394, which is also emerging as a serial bus interface standard, USB has the problem of slow transmission speed. [0004] Therefore, the USB2.0 standard was established, which attracted attention because it has low-bit compatibility with the previous USB1.1 standard, and at the same time, it can realize a data transfer rate of 480Mb...

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Problems solved by technology

[0009] However, such a method of manually arranging circuits and wiring has problems of long design period and high device cost compared with an efficient circuit design method using HDL (Hardware Description Language) circuit synthesis and automatic layout and wiring. At the same time, it also hinders the macro-unitization of data transfer control devices (physical layer circuits, logical layer circuits)

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