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Clock improvement for GPS timing system device and device thereof

A technology of GPS clock and timing system, applied in the field of global positioning system

Inactive Publication Date: 2006-03-15
BEIJING XINWEI TELECOM TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Existing methods cannot solve this problem, and a new method needs to be sought

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  • Clock improvement for GPS timing system device and device thereof
  • Clock improvement for GPS timing system device and device thereof
  • Clock improvement for GPS timing system device and device thereof

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Embodiment Construction

[0038] In the upgraded design, the GPS clock signal (GPS) is first sent to the complex programmable logic device CPLD (Complex Programmable Logic Device) 14 for processing, and the output signal (GPS_CPLD) is sent to the clock output unit. If the GPS is synchronized, the GPS has an output signal , then GPS_CPLD outputs GPS signal, if GPS signal disappears, GPS_CPLD outputs square wave signal.

[0039] like figure 2 and image 3 As shown, the internal GPS signal processing process of CPLD 14 is: GPS signal refers to the 100HZ clock signal (duty cycle is 20%~40%) that GPS receiver 11 outputs, and this signal will disappear when GPS is out of sync. The GPS signal is directly used as the synchronization signal of the base station. After the GPS is out of sync, the base station will be reset due to the disappearance of the GPS signal and cannot work normally. All users of this base station cannot work.

[0040] When GPS works normally (with GPS signal), such as Figure 4 As sho...

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Abstract

The invention relates to the method and device for modifying the timing in GPS timing system applied in system of synchronization code division multiple access (SCDMA). When GPS timing is in normal, the GPS signal is output. In the period of GPS out of synchronism, the timing output module of the CON board outputs the timing control signal. Base stations maintain the normal work continuously under the timing control signal outputted by the CON board. When normal GPS timing is recovered, the timing control signal is switched back and provided by the GPS again. If the time of GPS out of synchronism exceeds a certain period, the base station is stopped under control. The timing output module outputs the timing signal to the module of testing and treating GPS signal so as to complete digital phase locking and correct phase locked timing at any moment.

Description

technical field [0001] The invention relates to a global positioning system (GPS) in the communication field, in particular to a clock improvement method of the GPS timing system and its application in a synchronous code division multiple access system. Background technique [0002] In the synchronous code division multiple access (TD-SCDMA) system networking, generally each base station realizes the mutual synchronization through the timing system of GPS. The specific method is to set the working mode of GPS so that it can output a pulse signal with a period of 10ms, and the timing of sending and receiving of the base station is synchronized on this pulse signal. Since the pulse signals output by the GPS of each base station are synchronous, the transceivers between the base stations are completely synchronized. [0003] In the synchronous code division multiple access system, the synchronization methods of the base station include GPS synchronization and E1 synchronizatio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J13/02G01S5/02H04Q7/20H04B7/26H04L7/02H04W56/00
Inventor 吕建峰袁进林波
Owner BEIJING XINWEI TELECOM TECH
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