Low-power-consumption successive approximation analog-to-digital converter based on Split capacitor DAC

Abstract

The invention discloses a low-power-consumption successive approximation type analog-to-digital converter based on a Split capacitor DAC. The low-power-consumption successive approximation type analog-to-digital converter comprises a grid voltage bootstrapped switch module, the Split capacitor DAC, a comparator module and an SAR logic control module, the Split capacitance DAC is used for converting the digital code value from the SAR logic module into an analog voltage value through charge conservation and capacitance redistribution and outputting the analog voltage value to two input ends of the comparator; and the SAR logic control module is used for gating an either-or switch in the Split capacitor DAC to a corresponding voltage according to a result output by the comparator, so that the voltage values of the two output ends of the Split capacitor DAC are continuously close to each other, and finally a 12-bit digital output result is obtained. The SAR ADC is provided with the Split capacitor DAC with four C-2C structures, has smaller equivalent output capacitance and total capacitance, greatly reduces the power consumption and layout area of the SAR ADC, and reduces the requirement for the driving capability of a pre-stage circuit, thereby facilitating the improvement of the precision of a final product and the reduction of the cost; and meanwhile, the SAR ADC has a simpler circuit structure and a lower clock feed-through effect, so that the precision of the SAR ADC is improved.

Description

technical field [0001] The invention belongs to the technical field of analog converter (ADC) circuits, and in particular, relates to a low-power successive approximation analog-to-digital converter (SAR ADC) based on a split capacitor DAC. Background technique [0002] ADC is used to convert analog signals in nature into digital signals, and is an important part of various sensing circuits and signal acquisition circuits. Among them, SAR ADC is widely used in high power consumption requirements due to its low power consumption. In wearable devices and biomedical electronic devices, the power consumption limits the service life of these devices, and the accuracy limits the dynamic range of signal acquisition by these devices. In recent years, technologies to reduce the power consumption of SAR ADCs and improve the accuracy of SAR ADCs have received extensive attention. [0003] The traditional SAR ADC consists of a sampling switch, a capacitor DAC, a comparator and a SAR lo...

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Problems solved by technology

[0003] The traditional SAR ADC is composed of a sampling switch, a capacitor DAC, a comparator and a SAR logic circuit. The capacitance of the capacitor DAC increases exponentially with the accuracy of the ADC. When the resolution of the SAR ADC reaches 12 bits, the total capacitance of the capacitor DAC can be Up to hundreds of pF, bringing great dynamic power consumption

On the other hand, the gate voltage bootstrap switch used in the traditional SAR ADC has a large clock feedthrough, and at the same time, the dynamic comparator generates a huge kickback noise during operation, which greatly reduces the accuracy of the comparison results of the last few bits of the SAR ADC. accuracy, which reduces the accuracy of the SAR ADC

In response to these problems, no papers have proposed targeted solutions

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