Semi-parallel SC decoder implementation method and system based on FPGA
An implementation method and a decoder technology, which are applied in the field of FPGA-based semi-parallel SC decoder implementation methods and systems, can solve the problem of difficult decoder generation, increase the structural complexity of the semi-parallel SC decoder, and increase a small amount of decoding. code delay and other problems to achieve the effect of optimizing the structure
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[0053] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. For the step numbers in the following embodiments, it is only set for the convenience of illustration and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art sexual adjustment.
[0054] refer to figure 1 , the present invention provides a kind of semi-parallel SC decoder implementation method based on FPGA, and this method comprises the following steps:
[0055] S1. Setting the parameters of the decoder and initializing the part and update module and the reverse sequence rearrangement module to obtain the initialized decoder;
[0056] S11. Set the parameters of the decoder, and set the fixed-point scheme of the system. The parameters of the decoder include the code length of the polar code t...
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