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Differential input voltage charge scaling SARADC

A differential input and scaling technology, which is applied in electrical components, signal transmission systems, electrical signal transmission systems, etc., can solve the problem of inability to meet the design requirements of multi-bit high-speed and high-bandwidth ADCs, weak anti-interference ability of single-ended analog signal input, layout problems, etc. Problems such as inability to be highly matched can achieve the effect of improving linear performance, achieving high matching, and reducing area

Active Publication Date: 2022-05-31
QIANDU TONGCHIP XIAMEN MICROELECTRONICS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0017] The purpose of the present invention is to solve the problem that the commonly used multi-bit SAR_ADC circuit requires a large amount of capacitors to occupy the chip area and the layout cannot be highly matched, the single-ended analog signal input has weak anti-interference ability, and cannot meet the design requirements of multi-bit high-speed and high-bandwidth ADCs, and provides A differential input voltage charge scaling SAR_ADC

Method used

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specific Embodiment approach 1

[0086] Specific embodiment one: the following combination Figure 4 to Figure 15 This embodiment is described. A differential input voltage charge scaling SAR_ADC described in this embodiment includes a VREF voltage divider, a capacitor array DAC1, a capacitor array DAC2, a comparator, a SAR logic circuit and an N-bit register; a capacitor array DAC1 and a capacitor The array DAC2 adopts A+B bit combination DAC, the high A part is capacitive scaling, the low B part is the reference voltage scaling, N=A+B;

[0087] VREF voltage divider provides voltage for capacitor array DAC1 and capacitor array DAC2;

[0088] The capacitor array DAC1 and the capacitor array DAC2 are connected to the differential input signals VREF-AD and AD, where VREF is the system reference voltage and AD is the analog input signal;

[0089] The capacitor array DAC1 and the capacitor array DAC2 each output N voltage values ​​under the control of the SAR logic circuit. Each time the output voltages...

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Abstract

The invention discloses a differential input voltage charge scaling SARADC, belongs to the field of integrated circuits, and aims to solve the problem that a common multi-bit SARADC circuit needs a large number of capacitors to occupy the area of a chip. The circuit comprises a VREF voltage divider, a capacitor array DAC1, a capacitor array DAC2, a comparator, an SAR logic circuit and an N-bit register. The capacitor array DAC1 and the capacitor array DAC2 both adopt A + B bit combined DAC (Digital-to-Analog Converter), the high bit A part adopts capacitive scaling, the low bit B part adopts reference voltage scaling, and N is equal to A + B; the VREF voltage divider provides voltage for the capacitor array DAC1 and the capacitor array DAC2; differential input signals VREF-AD and AD are accessed to the capacitor array DAC1 and the capacitor array DAC2, the VREF is a system reference voltage, and the AD is an analog input signal; the capacitor array DAC1 and the capacitor array DAC2 respectively output voltage values for N times under the control of the SAR logic circuit, voltage VO1 and voltage VO2 output each time are subjected to difference comparison by the comparator, a comparison result each time is stored in the N-bit register as an effective bit, and a conversion result formed by N times of comparison is output.

Description

technical field [0001] The invention relates to a DAC circuit structure in a successive approximation register type (SAR) analog-to-digital converter (ADC), and belongs to the field of integrated circuits. Background technique [0002] One of the most important functions of signal processing is converting between analog and digital signals. The function of the analog-to-digital converter (ADC) is to convert the input analog signal into the corresponding binary digital character code. Since the analog signal is continuous in time and amplitude, while the digital code is discrete, the ADC system includes a signal sampling and holding process. The successive approximation type in the ADC type is essentially a binary search method. Taking the random number in 1-16 as an example, first determine whether the number is larger or smaller than 8. If the number is larger than 8, then whether it is larger than 12. larger or smaller than 12. The third search narrows down the range of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/08H03M1/46
CPCH03M1/08H03M1/462
Inventor 熊守芬李景虎赖杨林黄辉罗文宇郭赢寰涂航辉
Owner QIANDU TONGCHIP XIAMEN MICROELECTRONICS TECH CO LTD
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