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Test vector generation device and method

A test vector and generation device technology, which is applied in static memory, instruments, etc., can solve the problem of long test vector generation process, so as to solve the problem of long test vector generation process, save test costs, and save time for writing test vectors. Effect

Pending Publication Date: 2022-04-05
BEIJING AEROSPACE MEASUREMENT & CONTROL TECH
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Problems solved by technology

[0005] In order to solve the technical problem that the test vector generation process takes a long time, the application provides a test vector generation device and method

Method used

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  • Test vector generation device and method

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Embodiment Construction

[0057] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, but not all of them. Based on the embodiments in the present application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present application.

[0058] The first embodiment of the present application provides a test vector generation device, such as figure 1 , including: a function model module 101 , a test pattern algorithm module 102 , a test vector description module 103 , a test vector calculation module 104 and a vector data output module 105 .

[0059] Wherein, the functi...

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Abstract

The invention relates to a test vector generation device and method, and belongs to the technical field of integrated circuit testing. The test vector generation device comprises a function model module, a test graph algorithm module, a test vector description module, a test vector calculation module and a vector data output module. The function model module is used for establishing a test function model according to interface information acquired from the to-be-tested memory; the test graph algorithm module is used for providing test graph calculation logic; the test vector description module is used for providing vector data information of a storage address and providing pin definition; the test vector calculation module is used for calculating test vector data of each storage address of the to-be-tested memory; and the vector data output module is used for outputting test vector data. According to the device, the test vector data applied to the memory function test can be conveniently and quickly generated, the technical problem that the time of the test vector generation process is relatively long is solved, and the test efficiency of the memory is improved.

Description

technical field [0001] The present application relates to the technical field of integrated circuit testing, and in particular to a test vector generation device and method. Background technique [0002] Memory is an important category of integrated circuits and an important medium for realizing large-capacity data storage and transmission. It is mainly used to store data, instructions, programs and other information. With the continuous development of modern mobile storage technology and the storage market, semiconductor memory has become the most widely used storage device at present, and memory testing is becoming more and more important in the field of integrated circuit testing. On the one hand, the test of the memory can be used to judge whether the product quality is qualified, and on the other hand, the data obtained through the test can be used to improve the manufacturing process of the memory. [0003] The complexity of memory chips and the variety of memory cell...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/36G11C29/18
Inventor 闫丽琴冯建呈王占选郝改萍王振华殷晔潘国庆王石记
Owner BEIJING AEROSPACE MEASUREMENT & CONTROL TECH
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