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Design method of three-dimensional network-on-chip topological structure

An on-chip network and topology technology, applied in computing, computers, computing models, etc., can solve problems such as poor optimization results, low efficiency, and inability to intelligently design space exploration, etc., to achieve good optimization results, high search efficiency, and optimal search The effect of the result

Pending Publication Date: 2022-03-01
GUANGDONG UNIV OF TECH
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Problems solved by technology

[0006] The above-mentioned NoC topology design methods are all based on Mesh / 3D Mesh topology. However, the optimization algorithms used in these design methods are traditional greedy search and simulated annealing algorithms, which cannot intelligently explore the design space, resulting in low efficiency and poor optimization results.
In addition, these design methods are only optimized for one application scenario, and the resulting topology has certain limitations

Method used

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  • Design method of three-dimensional network-on-chip topological structure
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Embodiment

[0066] The specific implementation of the present invention will be further described below by taking the generation of a 4x4x4 three-dimensional network-on-chip topology structure as an example in conjunction with the accompanying drawings, but the implementation and protection of the present invention are not limited thereto.

[0067] Such as figure 1 , the specific implementation steps of the present invention are as follows: Step 1, the designer determines the network scale parameters and target application traffic characteristics; Step 2, initialization; Step 3, local search; Step 4, global search; Step 5, cyclic execution of steps 3 and 4 , until a solution that meets the design requirements is generated, and a low-latency, high-throughput 3D SWNoC topology is obtained; steps 1 to 4 are described in detail below.

[0068] Step 1, the designer determines the network scale parameters and target application traffic characteristics

[0069] For the 4x4x4 three-dimensional o...

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Abstract

The invention discloses a three-dimensional network-on-chip topological structure design method. The method comprises the following steps: determining a network scale parameter and a target application traffic characteristic; initializing a three-dimensional small-world on-chip network topology structure according to the network scale parameter, and calculating a corresponding network communication frequency; and respectively carrying out local search and global search for a single target application and a plurality of target applications until a design meeting a design requirement is generated, and obtaining a designed three-dimensional small-world network-on-chip topological structure. According to the method, the prediction function is learned based on the random forest regression by using the data generated by local search, the search result of the alternative initial design is evaluated by using the prediction function, and the next initial design is intelligently selected, so that the search efficiency is greatly improved, and a better search result is generated; according to the method, a plurality of application scenes are considered, the Pareto front is evaluated through the PHV evaluation index, the Pareto front is continuously improved, and finally design suitable for the multiple application scenes is generated.

Description

technical field [0001] The invention relates to the technical field of on-chip networks, in particular to a method for designing a three-dimensional on-chip network topology structure. Background technique [0002] Network-on-Chip (NoC) is the communication backbone between functional modules in System on Chip (SOC), and plays a decisive role in the overall performance of the system. NoC design includes network topology, router structure, routing algorithm, etc. The communication function of NoC mainly depends on the topology, which reflects the layout and connection of communication nodes in the chip, and has a great impact on network delay performance. The common NoC topology is Mesh topology (mesh topology). Mesh topology has good universality. However, for specific application scenarios, the general topology is obviously not the best choice. To this end, the researchers proposed the following NoC topology design method based on the Mesh topology: [0003] In 2006, Ogra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06K9/62G06N20/00
CPCG06F15/7807G06N20/00G06F18/24323
Inventor 陈嘉松熊晓明蔡述庭高怀恩詹瑞典
Owner GUANGDONG UNIV OF TECH
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