Design method of three-dimensional network-on-chip topological structure
An on-chip network and topology technology, applied in computing, computers, computing models, etc., can solve problems such as poor optimization results, low efficiency, and inability to intelligently design space exploration, etc., to achieve good optimization results, high search efficiency, and optimal search The effect of the result
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[0066] The specific implementation of the present invention will be further described below by taking the generation of a 4x4x4 three-dimensional network-on-chip topology structure as an example in conjunction with the accompanying drawings, but the implementation and protection of the present invention are not limited thereto.
[0067] Such as figure 1 , the specific implementation steps of the present invention are as follows: Step 1, the designer determines the network scale parameters and target application traffic characteristics; Step 2, initialization; Step 3, local search; Step 4, global search; Step 5, cyclic execution of steps 3 and 4 , until a solution that meets the design requirements is generated, and a low-latency, high-throughput 3D SWNoC topology is obtained; steps 1 to 4 are described in detail below.
[0068] Step 1, the designer determines the network scale parameters and target application traffic characteristics
[0069] For the 4x4x4 three-dimensional o...
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