Data storage processing method and device for iterative decoder

A technology for data storage and processing methods, applied in digital transmission systems, forward error control use, electrical components, etc., can solve the problems of full ping-pong RAM, reduced probability of successful decoding, large delay, etc., to save storage space , the storage structure is simple and easy to expand

Pending Publication Date: 2022-02-18
新岸线(北京)科技集团有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the OFDMA system, because the receiver has to process multiple user data at the same time, and the area of ​​the LDPC decoder is large, it generally allocates decoder resources to each user according to the principle of equal distribution. In the case of MCS, it is easy to cause the delay to be too large due to the large number of iterations of the LDPC decoder, and the two ping-pong RAMs are fully occupied.
If there is still data coming at this time, then it is necessary to add a new piece of RAM to modify the ping-pong structure; or terminate the iteration of LDPC in advance, which will reduce the probability of successful decoding

Method used

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  • Data storage processing method and device for iterative decoder
  • Data storage processing method and device for iterative decoder
  • Data storage processing method and device for iterative decoder

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0078] image 3 It is a schematic diagram of the easy-to-extend storage structure adopted by the LDPC decoder in Example 1 of the present invention. Such as image 3 As shown, the data processing flow of the LDPC decoder is as follows:

[0079] S301, during initialization, the data to be decoded is first written into the buffer ldpc_buffer, which is composed of 7 sub-RAMs, because the data of this RAM is only temporarily stored, so it does not need to participate in mathematical operations, and each point of it is For the original data, one sign bit plus five value bits represent a point, so each sub-RAM is 64X6*16. Since each row can save 32 bits, the sub-RAM depth is increased to 64 with the same capacity.

[0080] S302, ldpc_buffer uses in_wr, in_ring[6:0] to control which sub-RAM to write into. When the data to be decoded that reaches the number of cyclic sub-matrix T is written into ldpc_buffer, the write address will increase by one unit, and the ldpc_buffer has alrea...

Embodiment 2

[0112] 802.11n / ac / ax is currently the most popular indoor LAN solution. This protocol also uses LDPC encoding. The following uses LDPC in the WIFI protocol to illustrate this technical solution. The same solution is not only applicable to this protocol.

[0113] The main parameters of LDPC in the WIFI protocol are code length (N), code rate (R), and cyclic sub-matrix size (T). There are some differences between these parameters and EUHT's LDPC, mainly in that the size T of the cyclic sub-matrix does not have a multiple relationship between the maximum code length and the secondary code length. In order to facilitate hardware implementation, each data to be decoded is represented by 5 bits, and the sign bit is extended to 3 bits. Then the selection scheme of each storage unit of 802.11AC is as follows in Table 5:

[0114] Table 5 802.11AC LDPC encoding parameters and storage unit information

[0115]

[0116] It can be seen from Table 5 that the LDPC in the WIFI protocol h...

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Abstract

The invention provides a data storage processing method and device for an iterative decoder. The method comprises the following steps of: setting a cache memory for receiving and caching to-be-decoded data, and an operational memory for participating in intermediate calculation of a decoding arithmetic logic unit and caching related data; arranging a data path between the two memories for writing the to-be-decoded data stored in the cache memory into the operational memory; after the operational memory receives data with a code length, starting decoding; and when the decoding is completed or the maximum number of iterations is reached, writing the data cached in the cache memory into the operational memory in parallel so as to carry out subsequent decoding operation. By adopting the data storage processing method and device provided by the invention, the storage space can be saved, more to-be-decoded data can be cached, the storage structure is simple and easy to expand, and the data processing efficiency is not lower than that of a ping-pong storage structure.

Description

technical field [0001] The invention belongs to the technical field of wireless communication, and in particular relates to a data storage and processing method and device for an iterative decoder. Background technique [0002] The codec is an essential component unit in the communication system, and the decoder generally adopts iterative decoding based on efficiency and area considerations when implementing the ASIC, and most of them use the core decoding arithmetic logic unit plus the ping-pong storage structure. Realization, the architecture and processing flow of common iterative decoders are as follows figure 1 shown. The steps of a common iterative decoder processing flow are as follows: [0003] a) During initialization, the reference signals in_end, flag, dec_busy, and dec_suc_flag of the ping-pong control logic are all 0. The ping-pong control logic decides which RAM to be filled with the data to be decoded according to the flag. When the RAM is filled with data ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00
CPCH04L1/005H04L1/0045
Inventor 秦鹏
Owner 新岸线(北京)科技集团有限公司
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