Chip interconnection method, system, device and readable storage medium

Abstract

The present application proposes a chip interconnection method, system, device, and readable storage medium. The method includes: configuring the registers in the sending end chip to obtain the first register configuration information; The second register configuration information obtained after the registers in the chip are configured; connect with the receiving end chip according to the first register configuration information and the second register configuration information; obtain the connection status information with the receiving end chip; when detecting the connection status When the information satisfies the preset data transmission status, the data transmission with the receiving end chip is carried out. This application proposes a chip interconnection method, which can realize high-speed interconnection between two chips, solve the problem that the traditional PCIe device interconnection will interrupt one-way transmission, and avoid the need to build a new software architecture for the interconnection between two chips, resulting in low compatibility. problems, improve the efficiency of chip interconnection, and reduce the cost and resources of chip interconnection.

Description

technical field [0001] The present application relates to the technical field of communication transmission, in particular to a chip interconnection method, system, device and readable storage medium. Background technique [0002] The interconnection between chips is an indispensable part of communication transmission technology. The interconnection interface capability that a chip can provide often becomes a key factor in the design of communication systems. Therefore, the interconnection interface capability is also a key technical indicator for measuring chip capabilities. When designing a complex System-on-Chip (SoC) chip, it is necessary to plan its interconnection interface capabilities in advance to support a variety of applications in different scenarios. [0003] At present, existing chip interconnection methods mainly include the following methods: 1. PCIe RC is directly connected to EP; 2. Two PCIe RCs are connected through NTB or a PCIe switch with NTB function; ...

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Problems solved by technology

[0004] However, during the process of conceiving and implementing this application, the inventor found that the existing chip interconnection method has at least the following problems: PCIe device RC can be connected to EP or Switch, but the one-way transmission will be interrupted; and there is no direct connection between two RCs. Connected, there are restrictions on the connection of two SoC chips

If two SoC systems are connected through NTB or PCIe Switch with NTB function, a bridge chip is required, which increases the cost and leads to the problem of increased line and conversion delay

The car is connected through Gigabit Ethernet, the protocol itself is used for long-distance communication, and the delay is relatively high; at the same time, because the protocol adopts a seven-layer structure, the protocol overhead is relatively large

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