Test wafer, chip forming method and chip testing method

Abstract

The invention discloses a test wafer, a chip forming method and a chip testing method. The test wafer comprises a plurality of storage bare chips, each storage bare chip is provided with a plurality of test areas, and each test area comprises a control logic area and a pad area which are electrically connected; the control logic area is electrically connected with the corresponding storage bare chip, and the control logic area is integrated with control logic of a logic bare chip; and the pad area is used for carrying out a wafer probe CP test.

Description

technical field [0001] The present application relates to the field of semiconductor technology, in particular to a test wafer, a method for forming a chip and a method for testing a chip. Background technique [0002] The manufacturing process of integrated circuits can usually be divided into wafer manufacturing process, wafer testing, packaging and final testing. Before chip packaging, it is usually necessary to conduct an electrical performance test on the integrated circuit on the wafer to determine whether the integrated circuit is good, and the integrated circuit after the packaging process must undergo another electrical performance test to screen out the defects caused by the packaging process. Defective products caused by poor performance further improve the yield of the final product. In the related art, a wafer tester with several probes is usually used, the probes of the wafer tester are contacted with the integrated circuits of the wafer, and test signals are ...

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Problems solved by technology

[0003] However, this type of probe detection can only be performed on wafers that have been bonded. Once there is a defect in the memory wafer in the bonded wafer, the logic wafer bonded to it will also be scrapped.

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